Design and Characterization of STT-MRAM Periphery

Magnetic and spin-based technologies attract considerable interest for many applications:  nonvolatile data storage, low-power majority gate logic, neuromorphic computing. These devices are promising alternatives to traditional semiconductor-based devices as they offer built-in memory effect, low power consumption, scalability, reconfigurability. Spin Transfer Torque Magnetic Random-Access Memories (STT-MRAMs) are the first magnetic memory commercially available and fully compatible with silicon processes.  

This research internship addresses the characterization and design of in-house periphery assisting STT-MRAM subarrays. The circuitry is a key component within the memory macro, controlling the read and write operations happening within the memory subarray.

First, the student will analyse current versions of the developed periphery, characterising its key parameters (delay/power/energy) and carrying out sensitivity analysis on VDD dependence, load dependence, etc. Second, the student will propose improvements and re-design the modules to adapt to the in-house STT-MRAM devices. Third, the student will develop Analog-Mixed-Signal Models abstracting the behavior and power characteristics for more general studies.

At Imec, you will work within a diverse environment together with scientist from all around the globe. The team will welcome you and support you throughout the internship.

Background:  Electronics Engineering (Msc/BsC)

Profile: You like circuits and system modelling. You are proactive, and like to collaborate in a team project. You are comfortable programming.