Leuven | More than two weeks ago
Design and development of a sequencer in Python for extensive resistance and capacitance simulations of 3D interconnects
3D chip stacking is one of the leading technologies for increasing the functionality and the integration density of IC systems of different applications domains, as memory on memory, memory on logic, imagers, etc. This technology requires special vertical interconnect elements: the Through-Silicon Via or TSV, and the Hybrid Bonding pads. These vertical interconnects enable signal propagation and power distribution among the integrated circuits (IC) stacked one on top of the other. As for the ICs, these interconnect elements are also subjected to progressive reduction of their dimensions and are manufactured with different conductors and dielectrics; therefore, they need a careful prediction of their parasitic resistance and capacitance during the evaluation of new and scaled architectures to be adopted in future IC systems. Static solver simulations are currently used to extract 3D interconnect parasitics from interconnect models with many given dimensions and material properties as variables. Wide variable spaces need to be explored; therefore, this activity requires numerous simulation runs, each one with different values to be assigned to many model variables.
The goal of this project is to design and develop a python software, capable of running multiple sequential simulations of a static solver for predicting resistance and capacitance of 3D interconnect models in large variable spaces.
The input data will be a table where each row contains a set of numerical values to assign to the variables of each interconnect model; both tables and models are defined by the user.
The software will sequentially provide this data to the simulator, which for each input row of the table and for each model, will generate an output table with the extracted resistance and capacitance.
What you will do:
Learning from the project:
You will develop a software tool which will drive a state-of-the art simulator for multiple and unattended simulations runs. The software will be user-friendly, possibly with an easy GUI, and will be used to drive extensive resistance and capacitance simulations of 3D IC interconnect elements.
Who you are:
Bsc student in engineering or computer science;
Python knowledge is a must, experience in GUI implementation is a plus;
Basic Linux knowledge is a must;
You are available for minimum 3 months;
You have good written and verbal English skills.
Type of project: Internship
Required language: English
Required background: Engineering technology, computer science
Mentor: Michele Stucchi
Manager: For more information or for application, please contact Erik Bury (Erik.Bury@imec.be)