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/Job opportunities/Design of CMOS-based beamforming architectures for 6G

Design of CMOS-based beamforming architectures for 6G

PhD - Leuven | More than two weeks ago

You will design transceivers that operate above 100 GHz, preparing the world for 6G.

Wireless communication is ubiquitous in our life. Today, the most advanced wireless communication that we use in our smartphone makes uses of the 4G standard. Soon, the 5G standard will be deployed, featuring higher data rates and lower latencies. While operators and equipment manufacturers have their first 5G products ready, imec has already started research on 6G. 6G will feature even higher data rates than 5G, up to 100 Gbit/s and wireless communication with a latency well below 1 millisecond. This will serve applications such as high-resolution augmented reality or virtual reality, 3D holographic communication, ...

To enable this, a huge bandwidth is needed – much more than what 5G will provide. Such bandwidth is available above 100 GHz. However, operation at frequencies above 100 GHz is a serious challenge for CMOS as the cutoff frequency and maximum oscillation frequency of modern CMOS do not exceed 500 GHz and hence, little design margin is left. Moreover, CMOS has difficulties to generate much power above 100 GHz. This poses a serious limitation on the transmit power. At the receive side, the high operating frequency makes it difficult to design a low-noise amplifier with sufficiently low noise figure and sufficiently high gain. Further, wireless communication above 100 GHz suffers from a very high free-space path loss.

To overcome these limitations, beamforming can be used. Beamforming makes use of an antenna array from which the radiation pattern can be steered into a given direction. At the transmit side this is obtained by splitting the signal path over multiple paths that each contain a programmable phase shifter. At the antenna end, each transmit path contains a power amplifier that is connected to one antenna element of the antenna array. Dually, at the receive side, each antenna path is shifted in phase with an appropriate amount to virtually “orient” the antenna array into the direction of the received signal, after which all paths are combined.

To implement the beamforming functionality, that is to be combined with the transceiver, different architectures are possible. For example, the phase shifting and the signal combination (at receive side) can be done at RF frequencies or at baseband, after downconversion. Alternatively, the phase shift can be applied to the local oscillator signal that goes to the downconversion mixers. The goal of this PhD is to determine the optimal beamforming approach, taking into account the high operating frequency. You are going to use CMOS, although the last power amplification stage at the transmit side and the first – low noise – amplifier at the receive side might be designed in indium phosphide (InP) technology, but this outside the scope of this PhD.

Required background: Electrical Engineering

Type of work: 10% literature, 20% architectural study, 60% IC design, 10% experimental

Supervisor: Piet Wambacq

Daily advisor: Mark Ingels

The reference code for this position is 2021-111. Mention this reference code on your application form.

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