CMOS and beyond CMOS
Discover why imec is the premier R&D center for advanced logic & memory devices. anced logic & memory devices.
Connected health solutions
Explore the technologies that will power tomorrow’s wearable, implantable, ingestible and non-contact devices.
Life sciences
See how imec brings the power of chip technology to the world of healthcare.
Sensor solutions for IoT
Dive into innovative solutions for sensor networks, high speed networks and sensor technologies.
Artificial intelligence
Explore the possibilities and technologies of AI.
More expertises
Discover all our expertises.
Research
Be the first to reap the benefits of imec’s research by joining one of our programs or starting an exclusive bilateral collaboration.
Development
Build on our expertise for the design, prototyping and low-volume manufacturing of your innovative nanotech components and products.
Solutions
Use one of imec’s mature technologies for groundbreaking applications across a multitude of industries such as healthcare, agriculture and Industry 4.0.
Venturing and startups
Kick-start your business. Launch or expand your tech company by drawing on the funds and knowhow of imec’s ecosystem of tailored venturing support.
/Job opportunities/Design enablement and SoC level characterization of bit-array memory partitioning in 3D ICs

Design enablement and SoC level characterization of bit-array memory partitioning in 3D ICs

PhD - Leuven | More than two weeks ago

SRAM bit-cell and array design for 3D high-performance SoCs

Current Memory-on-Logic applications focus on the partitioning of either complete memory sub-systems (so memory arrays together with the memory controller logic) or the memory macros (the control logic remains on the logic die). In most of the designs the second solution exhibits better power, performance, area (PPA) but also cost, since the memory wafer processing can now be optimized though simplification of the BEOL and FEOL processing steps. The downside of the approach is that the number of 3D connections increases significantly. However, current Face-to-Face, Copper-to-Copper Hybrid bonding techniques allow to integrate 3D structures with a sub 1um pitch, which seems to be more than sufficient in partitioning intermediate cache memory layers even in advanced CMOS nodes (e.g. iN5). Such 3D integration technology motivates yet another memory partitioning scenario in which only bit-cell arrays are moved to another die. We expect that the number of 3D pins increases one order of the magnitude, however the expectations are that further PPAC benefits could be achieved. In this PhD the candidate will work on the design enablement of bit-array memory partitioning using current state of the art 3D implementation tools available at imec. Once the flow is ready, the required views (timing, power, geometry) for implementation of the bit-array partitioned memories will be proposed. Exhaustive SoC-level 3D place & route experiments will be carried on to provide in-depth analysis of different trade-offs linked to the proposed approach and when compared to more traditional Memory-on-Logic implementation. Cost aspects will be also covered using the existing cost models that need to be adapted for the above proposed partitioning scheme.



Required background: Masters in Electrical Engineering with CMOS design background, experienced in computer architecture

Type of work: Design enablement and SoC level characterization of bit-array memory partitioning in 3D ICs

Supervisor: Dragomir Milojevic

Daily advisor: Shairfe Muhammad Salahuddin, Rongmei Chen

The reference code for this position is 2021-044. Mention this reference code on your application form.

This website uses cookies for analytics purposes only without any commercial intent. Find out more here. Our privacy statement can be found here. Some content (videos, iframes, forms,...) on this website will only appear when you have accepted the cookies.