Master projects/internships - Leuven | More than two weeks ago
The purpose of this internship collaboration is to study the possibility of tuning the input stage transition level, and potential circuit design to improve the performance and reliability of current high-voltage tolerant I/O scheme.
I/O FET implementations beyond 5nm introduce the challenge with gate stack accommodation. I/O transistors suffer from dramatical drop of channel control capability due to small vertical sheet pitch. To meet the I/O voltage, such as 1.8V in many applications, the process solution of superlattice I/O FinFET has been proposed to integrate with core. However, dedicated I/O process efforts are still required, such as gate dielectric optimization for Si and Si/Ge superlattice . Besides the above challenges from the FEOL device geometries, the adaptions of I/O interfaces to the further scaling boosters, such as a fully back-side (BS) power delivery network (PDN), are required . A pure circuit solution has been proposed to realize a 1.8V(3xVDD) I/O circuit in a GAA NS technology without I/O process requirement , and its reliability was also evaluated. This provides great opportunities for system-technology co-optimization (STCO) evolution. However, some functions in GPIO are still missing in the proposed circuit scheme, and the performance of the circuit still needs to be improved. For example, the transition level of the input stage, PU/PD switching and the operational frequency. The purpose of this internship collaboration is to study the possibility of tuning the input stage transition level, and potential circuit design to improve the performance and reliability of current high-voltage tolerant I/O scheme.
 G. Hellings et al., VLSI, 2018  B. Chava et al. SPIE, 2019. W.-C. Chen et al VSLI, 2021
Type of work: Internship
Required degree: Master of Engineering Technology
Required background: Electrotechnics/Electrical Engineering
Imec allowance will be provided.