/Design of low-power, small-area neural read-out circuits for high-density multiple-channel neural recording

Design of low-power, small-area neural read-out circuits for high-density multiple-channel neural recording

Research & development - Leuven | More than two weeks ago

Enabling massive neural recording for brain-machine interface

Simultaneously recording the neuron activities in a brain is a challenge beyond the limits of existing techniques.  An invasive fully-integrated neural probe provides a way to record thousands of neurons. Such neural probe consists of tiny microelectrodes that can be implanted into the brain to acquire the neural signal through the electrode-tissue interface. The succeeding read-out (RO) circuits will pre-amplify, filter, and digitize the small neural signal (µV range) with a bandwidth ranging from 0.5Hz to 10kHz. In order to achieve a more intensive neural recording system, a more area- and power- efficiency RO circuit is a must. However, large unwanted signal (10s mV range) from electrode DC offset, motion artifact will deteriorate the small neural signal and eventually fail the recording.  Hence, the RO circuit should also be robust in the presence of the unwanted signal.  Thus, significant research efforts have been made to find the best potential architecture to meet the requirements mentioned above.

The goal of this master thesis is to model and design area- and power- efficient full-bandwidth neural signal read-out circuits that can be used together with a multitude of microelectrode arrays. The student will be involved in the literature study of different start-of-art designs, the feasibility study of the new-proposed RO architecture, and the model and design of the innovative analog circuits using the advanced CMOS technology.

Specific thesis objectives:

  • Study and understand the requirements behind the invasive neural signal acquisition from a multitude of electrodes.
  • Investigate by means of the start-of-art architectures for neural recording, have a deep understanding of each architecture.
  • Propose a  new read-out architecture which can achieve minimum area and power consumption that can be implemented in high-density CMOS neural probes.
  • Verify the feasibility of the proposed architecture by using i.e. Verilog A or AMS,  design the key building block of the architecture if possible.


  • Interest and enthusiasm in analog microelectronics
  • Knowledge of analog IC design principles
  • Knowledge of Cadence IC design tools (Spectre, Virtuoso, etc.)
  • Knowledge of circuit modeling using Verilog A, AMS etc. is a plus
  • Knowledge of Matlab

Type of project: Combination of internship and thesis

Duration: 9 months

Required degree: Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Xiaolin Yang (Xiaolin.Yang@imec.be) and Chutham Sawigun (Chutham.Sawigun@imec.be)

Imec allowance will be provided.