Design of a CML library for above 6GHz applications

Leuven - Master projects
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About a week ago

The purpose of this work is to design and layout a Current-Mode Logic (CML) library in the context of the SpaceFibre communications standard (6.25 Gbits/s serial link). In particular a Phase Frequency Detector (PFD) and a clock divider of a 6.25GHz PLL will be designed based on this library.

The purpose of this work is to design and layout a Current-Mode Logic (CML) library in the context of the SpaceFibre communications standard (6.25 Gbits/s serial link). In particular a Phase Frequency Detector (PFD) and a clock divider of a 6.25GHz PLL will be designed based on this library.

This design will be a part of the DARE65 library currently developed by IMEC IC-Link. The DARE65 platform (65nm technology) is developed in collaboration with the European Space Agency (ESA) and is the natural continuation of the DARE180 library developed during the past 15 years at IMEC.

Because the DARE65 platform is dedicated to space applications, all parts must be hardened against cosmic rays (neutron, proton, heavy ions...) existing outside the earth’s atmosphere.

 

The cosmic rays have mainly 2 effects on the CMOS circuit:

-         TID: the Total Ionization Dose result in an accumulation of charge trapped in the Silicon oxide interface.  These charges may induce leakage between devices and/or may shift the transistor threshold and/or increase the device leakage.

-         SEE: the Single Event Effects are due heavy ions passing through the silicon die and deposing electrical charge in the PN junction (from few tens of fC till few pC). This charge deposit can result in a latch-up and/or in a single-event transient and/or in a gate rupture...

The student can rely on in-house design knowledge: IMEC IC-Link has developed over the years specific tools and a design flow to harden designs for space applications:

-         layout specific rules

-         heavy ion electrical model

-         automated heavy ions check

-         edgeless transistor layout and simulation model

In order to go through the whole specification to layout flow, state of the art software is used. This requires the student to be present at imec on a regular basis. A basic, but solid understanding of analog design is required to reach the target on the practical design (including the post-layout simulation). Prior software knowledge is not required.

 

Software used:

         Cadence Virtuoso (schema & layout), Analog Design Environment XL & Spectre (simulation)

         Mentor Calibre (layout verification)

         Linux OS

Time allocation:

         20% studying literature

         50% design, simulation and post layout simulation

         30% layout

Type of project: Internship, Thesis, Combination of internship and thesis

Duration: 6-12 months

Required degree: Master of Engineering Technology, Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Giancarlo Franciscatto (Giancarlo.Franciscatto@imec.be) and Guillaume Pollissard (Guillaume.Pollissard.ext@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.

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