Design of a test vehicle to characterize a technology versus radiation

The purpose of this work is to design a generic test vehicle (i.e. complete chip intended for test/characterization) to fully characterize a technology versus radiations: both the Single Event Effect (SEE) and the Total Ionizing Dose (TID). This generic test vehicle will be demonstrated on a 180nm technology. A flow to perform an easy technology migration of this design will be established and defined. In particular this test vehicle will be able to extract/measure:

• The transistor degradation versus the total dose (TID): Vth shift, leakage
• The charge deposit by a heavy ion
• The duration of the SET pulse

This project evolves in the context of space mission where the cosmic rays are omnipresent. They have mainly 2 effects on the CMOS circuit:

-         TID: the Total Ionization Dose result in an accumulation of charge trapped in the Silicon oxide interface.  These charges may induce leakage between devices and/or may shift the transistor threshold and/or increase the device leakage.

-         SEE: the Single Event Effects are due heavy ions passing through the silicon die and deposing electrical charge in the PN junction (from few tens of fC till few pC). This charge deposit can result in a latch-up and/or in a single-event transient and/or in a gate rupture...

The student can rely on in-house design knowledge: IMEC IC-Link has developed over the years specific tools and a design flow to harden designs for space applications:

-         layout specific rules

-         heavy ion electrical model

-         automated heavy ions check

-         edgeless transistor layout and simulation model

In order to go through the whole specification to layout flow, state of the art software is used. This requires the student to be present at imec on a regular basis. A basic, but solid understanding of analog design is required to reach the target on the practical design (including the post-layout simulation). Prior software knowledge is not required.

Software used:

•         Cadence Virtuoso (schema & layout), Analog Design Environment XL & Spectre (simulation)

•         Mentor Calibre (layout verification)

•         Linux OS

Time allocation:

•         10% studying literature

•         60% design, simulation and post layout simulation

•         30% layout