PhD - Leuven | More than two weeks ago
Design-for-Reliability paradigms based on physics-based system-level electromigration modelling approaches.
Electromigration has been a major reliability concern for nano-interconnects in CMOS applications. With further CMOS miniaturization, the cross-sectional area of nano-interconnects is further scaled resulting in an increase of current densities. In this context, it has been shown that the maximum current that the copper interconnects can withstand degrades abruptly at scaled linewidths, predicting increased susceptibility to electromigration. The standard flow for electromigration checks in the design phase is typically based on comparing the electrical current values in circuit segments with current limits obtained from electromigration tests on single isolated interconnects. However, this is a simplistic approach and generally results in conservative designs because it ignores the interactions amongst interconnects during system aging. To this aim, statistical modelling has been proposed to link single interconnect metrics to system level metrics [1,2]. Nevertheless, crucial aspects such as the impact of system architecture e.g. circuit redundancy, interconnectivity, and layout require architecture-specific modelling. For instance, prediction of void location in a circuit requires determination of electromigration induced mechanical stress throughout the circuit which is only possible using physics-based modelling approaches. Also, the electromigration aging depends on system workload allocation, activity factors, temperature variations across and within system components and other operational metrics.
Recently, physics-based system-level electromigration characterization and modelling approaches have been emerging that can predict the electromigration induced voiding and its impact on system operation more accurately [3-8]. However, incorporation of such models into robust Design-for-Reliability approaches at the system-level in such a way that could be compatible with electronic design automation tools with feasible computational cost, remains to be a challenge. In this PhD position, the researcher will conduct cross-team research within the reliability and the CMOS design teams to explore paradigms that allow system-level physics-based electromigration modelling to be integrated into CMOS design flows and possibly also address emerging challenges such as the drastic thermal implications of high-power densities on interconnect reliability.
 J. Kitchin. 1995. Statistical electromigration budgeting for reliable design and verification in a 300-mhz microprocessor. In Proceedings of the 1995 Symposium on VLSI Circuits.
 B. Li, P.S. McLaughlin, J. P. Bickford, P. Habitz, D. Netrabile, and T. D. Sullivan. 2011. Statistical evaluation of electromigration reliability at chip level. IEEE Transactions on Device and Materials Reliability 11, 1, (Mar 2011).
 M-H Lin and A.S. Oates. 2016. Electromigration failure of circuit interconnects, In Proceedings of the 2016 IEEE International Reliability Physics Symposium, IRPS 2016.
 C. Zhou, R. Wong, Shi-Jie Wen, and C. H. Kim. 2018. Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points. In Proceedings of the 2018 Symposium on VLSI Technology.
 N. Pande, C. Zhou, M-H Lin, R. Fung, R. Wong, S-J Wen, and C. H. Kim. 2019. Characterizing electromigration effects in a 16nm finfet process using a circuit based test vehicle. In Proceedings of the 2019 IEEE International Electron Device Meeting, IEDM 2019.
 C. Zhou, R. Fung, S-J Wen, R. Wong, and C. H. Kim. 2020. Electromigration effects in power grids characterized from a 65 nm test chip. IEEE Transactions on Device and Materials Reliability 20, 1, (Mar, 2020).
 F. N. Najm, V. Sukharev. 2019. Efficient simulation of electromigration damage in large chip power grids using accurate physical models. IRPS 2019.
 H. Zahedmanesh, I. Ciofi, O. Zografos, M. Badaroglu, K. Croes, 2021, A novel system-level physics-based electromigration modelling framework: application to the power delivery network.
Type of work: 10% literature and technological study, 40% numerical modelling, 40% design analysis, 10% experimental characterization
Focus: Circuit design, modelling, post P&R analysis, Power Delivery Network (PDN) optimization and analysis
Promotor: Prof. Dragomir Milojevic, Dr. Houman Zahedmanesh
Manager: Ivan Ciofi (imec)
Daily advisors: Dr. Houman Zahedmanesh
The reference code for this position is 2022-122. Mention this reference code on your application form.