Design Space Exploration for High Performance AIMC Based Accelerator

Design Space Exploration for High Performance AIMC Based Accelerator

Debjyoti Bhattacharjee, Peter Debacker, Arindam Mallik

With the massive growth in size of neural networks, energy consumption of neural network inference has also risen. From a computation perspective, quantization techniques are used widely for lowering computational complexity. From the hardware perspective, analog-in-memory computing (AiMC) based solutions have grown popular in recent years. AiMC based solutions have extremely high energy efficiency of the order of 1000Tops/W.

The performance of an accelerator is heavily dependent on the choice of design parameters as well the technology parameters. Given the wide range of choices available for these parameters, it becomes imperative to systematically determine which design parameters have the highest impact overall accelerator efficiency.

The specific goals of this project are as follows:

1. Use a proprietary design space exploration framework to perform a sensitivity analysis of the design parameters.
2. Report the results for neural network workload from MLPerf benchmarks.
3. Benchmark the results against existing state-of-the-art neural network accelerators.

Skills:

Mandatory: Computer Architecture, Python, familiarity with deep neural networks.

Optional: Pytorch, Familiarity with NN Accelerators