Design–Technology Co-optimization (DTCO) researcher
What you will do
As DTCO researcher, you will help drive imec’s technology and architecture roadmap to build the semiconductor technology of the near and far away future.
- You will evaluate the impact of device, backend and patterning choices on SoC design. You do so in order to guide future technology development by regular scaling and by leveraging hybrid integration solutions. That way you scale specific parts of an SoC more efficiently
- You will use your knowledge of physical implementation and sign-off tools to assess power, performance and area of various technology options (devices, standard cell architectures, interconnect) at place and routed SoC (subblock) level
- You will evaluate at circuit level various SoC subcircuits like critical paths, clk trees etc. at the outset of different device and back end options.
- You will go beyond the current capabilities of the tools and work together with EDA partners to get tools ready for the future nodes, e.g. to enable novel power grid solutions, or 3D stacked designs etc.
What we do for you
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits.
Who you are
- The ideal candidate will have a PhD in Electronics, or a master with at least 3 years relevant industrial experience in physical implementation.
- You have a background of digital implementation and SoC architecture for one or more application domains (Mobile, Server, …). Also, you can make specifications for different parts of SoC in different market spaces.
- Experience with synthesis and physical implementation tool flows(Cadence Innovus, or Synopsys ICC) is a must
- You have worked in multi-disciplinary teams, ideally both interacting with hardware designers as well as EDA vendors and foundry partners.
- Since you will work in our exciting multi-cultural environment, you speak and write English very well.