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/Job opportunities/Design technology co-optimization of emerging storage class memories

Design technology co-optimization of emerging storage class memories

PhD - Leuven | More than two weeks ago

Designing Memory and Storage Systems for the Future

As a consequence of our increasing reliance on information nowadays, both for home and personal use along with business and professional needs, more and more data is being generated, processed, moved, stored, and retained in multiple copies for longer periods of time. Research has shown that the biggest performance bottleneck with popular smart-phone apps such as Facebook and Google Maps is, in fact, how fast they can read and write a device’s data storage. This suggests that without solving the ‘Memory Bottleneck’, the benefits of new networks and processors will be limited. Aggressive technology scaling has also, placed limitations on current data storage technologies.

 

Thus, several new Non-Volatile Memory (NVM) technologies and corresponding selector devices are currently being investigated to eventually satisfy the need for higher storage capacity, system performance, lower power consumption, smaller form factor, lower system costs and long dataretention capability. Phase Change RAM (PC-RAM) and Magneto-Resistive RAM (MRAM) are among the more mature NVM technologies. Spin Orbit Torque (SOT) MRAM and Voltage Controlled Magnetic Anisotropy (VCMA) MRAM are some of the more recent NVMs with interesting characteristics. However, replacing the heavily optimized existing storage memory design architectures is easier said than done. Crossbar 3D architectures with NV memory elements have emerged as the primary challenger to existing storage technology. These highly dense crossbar 3D architectures of emerging NVMs need heavy technology optimizations and radical new bit-cells, ultra-low sensing schemes, low leakage and low power architecture solutions to be effective. Each technology also comes with a set of inherent flaws, like write endurance limitation, or high access latency, etc. The plethora of challenges present a vast design exploration space.

 

Research Target: 

Several concepts of non-volatile memories mentioned above being investigated at imec as potential candidates for both embedded and storage class domains. In this PhD thesis, the different technologies will first be compared and evaluated from a technology perspective for the targeted platforms and application domains. The major part of the PhD will focus on the design and analysis of the SCM array to enable low power memory architectures that can tolerate the innate variability of resistive devices for large arrays/blocks and large voltage budgets to ensure write without disturb. Finally, due the shrinking space between Main Memory [DRAM] and Storage [NAND flash SSD], It is also important to perform an exhaustive pareto-optimization between the performance, density and power for such architectures. This may involve the PhD student to assist in the evaluation the 3D SCM Macros at the system level and characterize them with respect to performance requirements, block level definition, workloads and other key features. In order to realize this, a close interaction between circuit and system experts will be required.



Required background: Electrical Engineering

Type of work: 55% circuit design, 15% system design, 10% behaviour modelling, 10% software, 10% literature

Supervisor: Wim Dehaene

Co-supervisor: Jan Van Houdt

Daily advisor: Manu Perumkunnil, Mohit Gupta

The reference code for this position is 2021-018. Mention this reference code on your application form.

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