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/Job opportunities/Design-Technology Co-optimization for High-Yield SRAM in sub-7nm Nodes

Design-Technology Co-optimization for High-Yield SRAM in sub-7nm Nodes

PhD - Leuven | More than two weeks ago

SRAM compiler design to evaluate imec CMOS technologies and guide process development

The impressive growth of semiconductor industry in the past few decades has been driven by the CMOS technology scaling. Miniaturizing the CMOS devices provides larger integration density, higher performance while lower the power consumption. However, SRAM performance and stability are greatly compromised due to the process induced variability in advanced technology nodes. The high resistive word-lines and bit-lines further degrades the SRAM performance and stability. Emerging devices such as nanowire, nanosheet, fork-sheet, complementary FET, NCFET, magnetic devices have been perceived as the promising candidates for SRAM bit-cell design in advanced technology nodes. Various metallization options such as buried power rails have been explored to improve SRAM performance and stability.

In this work the candidate will interact with different imec groups working on technology development, material selection, TCAD simulation, and design to identify the challenges and opportunities of SRAM design. The primary objectives are to come up with SRAM bit-cell design, array and periphery logic design, and SRAM compiler development for various device and process technologies. The SRAM complier developed in the work will drive the imec logic technology roadmap. ​



Required background: Electrical engineering with CMOS design background, experienced in SRAM, python programming would help

Type of work: 20% literature, 40% modelling, 40% design

Supervisor: Wim Dehaene

Daily advisor: Shairfe Muhammad Salahuddin, Pieter Weckx

The reference code for this position is 2020-051. Mention this reference code on your application form.