/Design Technology Co-Optimization of Logic device for Memory Application

Design Technology Co-Optimization of Logic device for Memory Application

Leuven | More than two weeks ago

Circuit design and tape-out for advanced Logic and Memory applications
We are living today in a Big Data Era, characterized by an enormous abundance of information useful for science or business. Extensive Volume and Variety of data are constantly generated at fast Velocity, with very low information density and potentially great Value provided that appropriate data processing is applied to extract the relevant information for applications. Data storage, data analysis and data visualization are examples of the complex tasks required to fully leverage information mining.  While the computational power constantly increases with time, the poor performance of data movement across the system remains one of the main computer architecture challenges.

Convergence between logic and Memory is crucial to extending the performance of advanced systems. In the context of advanced Storage Class Memory and Non Volatile Memory, this project aims at the exploration of innovative transistor devices and test chip design for Memory periphery to boost the performance of data transmission between different parts of the chip.

In this work, the candidate will interact with different imec groups working to identify technology for memory periphery, compact modelling, circuit design, test chip design and measurement. 

Type of project: Combination of internship and thesis, Thesis

Required degree: Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Alessio Spessot (Alessio.Spessot@imec.be) and Shairfe Muhammad Salahuddin (Shairfe.Muhammad.Salahuddin@imec.be)