/Design-Technology Co-optimization for Low-Voltage SRAM in sub-3nm Nodes

Design-Technology Co-optimization for Low-Voltage SRAM in sub-3nm Nodes

Leuven | More than two weeks ago

Explore SRAM technology for next generation CMOS nodes
Static Random-Access Memory (SRAM) is the most common embedded-memory and major building block in CMOS ICs. A significant percentage of the total area and power for digital chips are occupied by SRAM. Thus, designing a high density and low power SRAM is critical. The subthreshold digital circuit design has emerged as a solution to achieve energy-efficient design for system-on-chips (SoC). However, SRAM operation is severely affected by the process, voltage, temperature (PVT) variations, and increased leakage current with aggressively scaling supply voltage to the near- or sub-threshold regime. Furthermore, the SRAM performance and stability are also degraded due to process-induced variability with miniaturizing the CMOS devices in advanced technology nodes.  As a result, reducing the minimum functional supply voltage (Vmin) is the key to achieving low power SRAM design in sub-3nm nodes. 

In this work, the candidate will interact with different imec groups working on technology development, material selection, TCAD simulation, compact modelling, and circuit design to identify the challenges and opportunities of low power SRAM design. The primary objectives are to come up with memory bit-cell architecture, array design, and read/write assist circuit design. The design-technology co-optimization architectures used in the work will drive the imec logic and memory technology roadmap. 

Type of project: Internship, Thesis, Combination of internship and thesis

Required degree: Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Samantha Liu (Samantha.Liu@imec.be)