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/Job opportunities/Design – Technology co-optimization researcher

Design – Technology co-optimization researcher

Research & development - Leuven | More than two weeks ago

Place and Route level exploration of 2nm technology and beyond

Design – Technology co-optimization researcher

What you will do

  • You will evaluate the impact of device, backend and patterning choices on SoC design, in order to guide future technology development, both by regular scaling as by leveraging hybrid integration solutions to scale specific parts of an SoC more efficiently
    You will use your knowledge of physical implementation and sign-off tools to assess power, performance, and area of various technology options (devices, standard cell architectures, interconnect) at place and routed SoC (subblock) level
  • You will evaluate at circuit level various SoC subcircuits like critical paths, clk trees etc. at the outset of different device and back end options.
  • You will go beyond the current capabilities of the tools and work together with EDA partners to get tools ready for the future nodes, e.g. to enable novel power grid solutions, or 3D stacked designs etc.
  • You will interact with universities on development of new micro-architecture concepts that leverage novel technology capabilities such as 3DIC partitioning, specialty components amongst others.
  • In this role, you will have thé opportunity to interact closely with circuit designers, device experts and process integration engineers as well as major foundry, fabless and EDA partners in imec’s eco-system.
  • You will help drive imec’s technology and architecture roadmap to build the semiconductor technology of the near and far away future.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow. 
We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits.

Who you are

  • You obtained a PhD in Electronics, or a master’s degree with at least 3 years relevant industrial experience in physical implementation.
  • You have a background of digital implementation and SoC architecture for one or more application domains (Mobile, Server, …) and can make specification for different parts of SoC in different market spaces.
  • You have worked in multi-disciplinary teams, ideally both interacting with hardware designers as well as EDA vendors and foundry partners.
  • You have a critical mindset, eager to explore new challenges in the future andevolve together with the changing R&D demands.
  • Experience with synthesis and physical implementation tool flows (Cadence Innovus, or Synopsys ICC) is a must.
  • Experience with power signoff (e.g. Cadence Voltus) and design closure is a plus (Mutli-mode-multi-corner/ ECO flow).
  • You are an open and constructive team player
  • You actively look for solutions to problems and are driven by delivering results on time.
  • Given the international character of imec, a fluent knowledge of English is necessary. 


Apply online at

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