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/Job opportunities/Design of an ultra-low power ISFET readout front-end

Design of an ultra-low power ISFET readout front-end

Research & development - Leuven | More than two weeks ago

ingestibles enabling data-driven food and health research
One of the keys to a healthy life, is nutrition. But what exactly constitutes ‘healthy’ food for a specific person? To answer that question, you need to measure and analyze the processes inside the complex human digestive system. Digestive processes are hard to examine. Almost all known methods involve a prolonged endoscopy, which is uncomfortable for the patient and only allows for a relatively short-term observation in one specific place of the stomach. That is why ingestible sensors will benefit patients as well as doctors. Imec is developing technology that will analyze the mechanical, chemical, and electrical processes in the gut.

Promising sensors inside ingestible solutions are the ion-sensitive field-effect transistor (ISFET) and chemical field-effect transistor (chemFET). When properly biased, these sensors translate an (electro)chemical modality into an electrical modality. To enable sensor operation and bridge the gap between the sensor and ADC, an analog front-end is needed. Since ingestible systems have a limited power budget, limiting power consumption is a must, and the typical large current biasing of these sensors must be questioned.

After studying the current literature on ultra-low power ISFET readouts, the first goal is to envision an appropriate architecture that fits the requirements and alleviates the problems that come with previous ultra-low power implementation. Secondly, a transistor level design and verification cycle will concretize the front-end. Lastly, layout of the transistor level schematic will prepare the front-end for a potential tape-out.  

For ISFET experiments you will have access to our electronic lab. For design, verification, and layout we use the industry standard tools (Cadence Virtuoso, Mentor Graphics Calibre) and have high computational power servers available.

Content of the thesis:

  • Literature study/theoretical (30%)
  • Architecture definition & transistor level design (60%)
  • Layout (10%)

Type of project: Internship, Thesis, Combination of internship and thesis

Duration: up to 9 months

Required degree: Master of Science, Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Wim Sijbers (

Imec allowance will be provided for students studying at a non-Belgian university.