/Development of IGZO-based metal-semiconductor (MeSFET) transistors for selector applications

Development of IGZO-based metal-semiconductor (MeSFET) transistors for selector applications

Leuven | More than two weeks ago

Electrical characterization and TCAD simulation of Schottky barrier MeSFET devices based on oxide semiconductors for unconventional cross-point architectures


Cross-point architecture is a promising option to enable high-density low-cost memory solutions. It consists of a dense array of memory elements (MEs) integrated in the back-end-of-line (BEOL) [1]. This requires a highly non-linear two-terminal BEOL-compatible selector (1S) device in series with the ME (1R). The resulting 1S1R configuration is able to effectively address the selected cell and suppress the sneak current paths through the unselected ones. In the case of a unipolar memory technology (meaning, it can be operated with a single polarity), such as Phase-Change Memory (PCM) or Voltage-Controlled Magnetic Anisotropy (VCMA) magnetic memory, the role of the selector can be played by a simple diode [2].


The requirement for BEOL compatibility limits the list of available materials. One suitable option is to rely on amorphous oxide semiconductors, such as InGaZnO (IGZO), that can be deposited at low thermal budget [3]. In this context, imec has developed a high-performance IGZO Schottky diode, targeting VCMA application [4].


Most recently, by exploiting IGZO properties, we are exploring a novel crosspoint array architecture capable of significantly enhancing the read margin of an 1S1R architecture. This breakthrough is enabled by the use of a MEtal-Semiconductor Field-Effect Transistor (MeSFET), which consists of a semiconductor material directly in contact with a high-workfunction metal to form a Schottky barrier (instead of gate oxide in a classical MOSFET). As a result, this device can be used simultaneously as a transistor in a horizontal direction and a diode in a vertical direction. This allows to implement a novel array structure with unique properties.



This project will focus on a development of a MeSFET transistor with IGZO channel. This involves electrical characterization of fabricated devices, analysis of the obtained data and device simulation to support the results. The goal is to establish the impact of various factors (device dimensions, thickness, anneal conditions) on MeSFET parameters. The work will involve a combination of experimental and modelling activities, that can be tailored to candidate’s interests and experience.


  • Deep knowledge of semiconductor device physics
  • Data analysis skills, working knowledge of Python (or other scripting language)
  • Familiarity with circuit simulation (SPICE) and/or TCAD tools is a plus
  • Experience with electrical characterization instrumentation is a plus

[1] G. W. Burr et al., “Access devices for 3D crosspoint memory,” Journal of Vacuum Science & Technology B, vol. 32, no. 4, p. 040802, Jul. 2014,  doi: 10.1116/1.4889999.

[2] S. H. Lee et al., “Highly productive PCRAM technology platform and full chip operation: Based on 4F2 (84nm pitch) cell scheme for 1 Gb and beyond,” in 2011 International Electron Devices Meeting, Dec. 2011, p. 3.3.1-3.3.4. doi: 10.1109/IEDM.2011.6131480.

[3] S. Subhechha et al., “Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm,” in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022, pp. 292–293. doi: 10.1109/VLSITechnologyandCir46769.2022.9830448.

[4] S. H. Sharifi et al., “Sub-µm a-IGZO, Fully integrated, Process improved, Vertical diode for Crosspoint arrays,” in 2020 IEEE International Memory Workshop (IMW), May 2020, pp. 1–4. doi: 10.1109/IMW48823.2020.9108124.



Type of project: Combination of internship and thesis

Duration: 3-9 months

Required degree: Master of Science, Master of Engineering Science

Required background: Nanoscience & Nanotechnology, Electrotechnics/Electrical Engineering, Physics

Supervising scientist(s): For further information or for application, please contact: Taras Ravsher (Taras.Ravsher@imec.be) and Andrea Fantini (Andrea.Fantini@imec.be)

Imec allowance will be provided.

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