Development of Low Power and High-Speed SRAM Compiler

Topic description:

Static Random-Access Memories (SRAMs) have become a standard component embedded in all System-on-Chip (SoC), Application-Specific Integrated Circuit (ASIC), and microprocessor designs. For instance, in modern microprocessors, the on-chip SRAM caches consume about half of the total chip area, 60%-90% of the transistor counts and large percentage of power budget. Hence, memory designs play a significant role in overall system performance and costs, so optimization is important. However, manual design and optimization is too time consuming. The regular structure of memories leads well to automation that produces size and configuration variations quickly but developing this with multiple technologies and tool methodologies is challenging. The project aims in developing a python-based SRAM compiler that automate the layout generation and the PPA estimation for given SRAM macro size and different simulation parameter values from the user.

In this work the candidate will interact with different imec groups working on technology development, material selection, TCAD simulation, and design to identify the challenges and opportunities of SRAM design. The primary objectives are to develop SRAM compiler that will be used to generate the layout and estimate the PPA based on a given SRAM macro size and simulation parameter values, input by the user, with the option of choosing between low power vs high-speed SRAM macro. The SRAM compiler developed in the work will drive the imec logic technology roadmap.