/Development of power gating circuitry model

Development of power gating circuitry model

Master projects/internships - Leuven | More than two weeks ago

Develop an electrical equivalent model for power gating circuitry, including the chip power pads, power gating switches, active circuitry, PDN etc., aiming to facilitate the evaluation of trade-offs of novel technology assumptions across the stack. 

This internship targets to develop an electrical equivalent model for power gating circuitry, including the chip power pads, power gating switches, active circuitry, PDN etc., aiming to facilitate the evaluation of trade-offs of various technology assumptions across the stack. Advanced digital ICs require fine-grained power gating schemes than the conventional IP-based coarse power gating circuitry placement and design and hence it is critical to have a framework to model the power gating scheme, which can emulate design-dependent constraints. This work is primarily aimed towards, but not limited to porting the PPA evaluation of novel FS/BS power switching schemes to block/system level. The framework could be based in Python/Matlab/Simulink environment with coupled inputs from circuit simulators like spectre.

Type of Project: Combination of internship and thesis 

Master's degree: Master of Engineering Technology 

Master program: Electrotechnics/Electrical Engineering 

Duration: 6 - 9 months 

For more information or application, please contact Priya Venugopal (priya.venugopal@imec.be)

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