Dielectric reliability in 3-D highly scaled interconnects

Leuven - PhD
|
More than two weeks ago

Make sure that the electrical signals in 3-D stacked IC's travel from chip to chip on safe and long-lasting interconnect elevators

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The 3‑D integration of chips by stacking them one on top of the other has been adopted by the industry as an alternative solution to increase the transistors and interconnects density.

The vertical connections between stacked dies are a key element of this technology. Two common vertical interconnect elements are pad-to-pad connections in hybrid bonding technology and Through Silicon Vias, or TSV.

Hybrid bonding connections are used in face-to-face chip stacking. They are achieved by copper pads designed and patterned in the outer copper interconnect layers of the chips to be stacked together, as shown in the top part of the figure below. When bonding is performed, three interfaces are created: dielectric/dielectric, metal/metal and metal/dielectric, hence the name hybrid-bonding.

A Through-Silicon Via consists of a vertical conductor, usually copper, entirely crossing the Si substrate of the stacked dies. The conductor is isolated from the substrate by a thin silicon oxide dielectric; with Cu as conductor, a barrier layer between Cu and oxide is necessary to prevent diffusion of Cu atoms reaching the dielectric and the Si substrate. TSVs are used to make electrical signals and power distribution available at the backside of a die, thus enabling back-to-face stacking scheme and providing electrical accessibility at the top of the face-to-face scheme, as shown in the figure below.

Vertical interconnections must provide a reliable signal and power distribution among the circuit blocks present in each die of the stack. Other than low parasitic resistance and capacitance, electrical isolation between adjacent hybrid bonding pads and between TSV and substrate must be guaranteed, to prevent leakage current. For the TSV, the proximity to transistor devices present in the substrate is an additional concern for Cu diffusion from a defective barrier, which can degrade transistor functionality and performance.

The continuous demand of higher interconnect density drives dimension and pitch scaling of these vertical interconnections to the submicron range. Unfortunately, this brings serious reliability concerns.

For hybrid bonding pads, smaller spacing between them increases the possibility of preferential leakage current paths formation in the horizontal interfaces of the dielectric layers between the pads, from surface contaminants during the processing of metal and dielectric layers before the bonding; the electric field between the pads also increases, if the voltage does not scale with pad spacing; misalignment between the pads, due to poor alignment accuracy, further increases the field, as represented in the right-bottom part of the figure.

For the TSV, smaller submicron diameters of the silicon cavity imply to deposit dielectric and barrier layers with smaller thicknesses, to mitigate the reduction of the Cu diameter with scaling;  consequent risks are pinholes in the barrier and nanometer-range thick dielectrics in high electric fields, very favorable conditions for Cu diffusion in the dielectric itself and in the substrate.

PhD dielectric reliability

Hybrid bonding sequence with the resulting vertical connections of top and bottom pads and with the implementation of a TSV to enable the electrical access from the top of the stack. Adjacent pads could suffer from leakage currents caused by Cu residuals on dielectric surfaces; high electric fields caused by pad misalignment could further enhance Cu diffusion and lower the breakdown voltage between the pads. Pinholes in the TSV barrier and high electric fields in very thin dielectric liner would cause Cu diffusion to the transistors nearby.

The aim of this PhD is to investigate, evaluate and predict the impact these issues on dielectric reliability of these vertical interconnects, and to help identifying possible mitigation strategies.

In more details, the following achievements are expected:

  • Identification of the possible failure modes and relative mechanisms with different dielectric materials, architectures and dimensions of hybrid bonding pads and nano-scale TSVs;
  • Building dielectric reliability models calibrated and validated with experimental data measured on suitable test structures, which would allow lifetime predictions in function of architecture, dimensions, dielectric material properties of the vertical interconnects;
  • Identifying by the model the suitable architecture, dimensions, dielectric material properties which guarantees the respect of lifetime specs by the vertical interconnects.

    To reach these goals, the following activities are foreseen:
  • Deep understanding of the hybrid bonding and TSV technologies and their applications;
  • Dielectric reliability characterization of hybrid bonding interconnects and nano-TSVs by electrical measurements, failure analysis and physical analysis of experimental test structures, to identify possible dielectric failure modes and relative mechanisms;
  • Design of new test structures to assess dielectric reliability in TSVs and hybrid bonding pads;
  • Statistical data analysis of reliability data extracted from electrical characterization;
  • Building of analytical/computer models for dielectric lifetime predictions;
  • Interaction with 3-D process integration engineers to provide them feedback on the reliability characterization results.

    Supervising scientists:
    E. Chery (Emmanuel.Chery@imec.be)
    M. Stucchi (Michele.Stucchi@imec.be)

Required background: Material Science, Engineering Technology, Si Process Technology

 

Type of work: 40% Experimental, 20% Interpretation, 20% Literature, 20% Modeling and simulations

Supervisor: Ingrid De Wolf

Daily advisor: Michele Stucchi, Emmanuel Chery

The reference code for this position is 2020-030. Mention this reference code on your application form.

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