/Digital design and technology optimization using hybrid CMOS 2.0

Digital design and technology optimization using hybrid CMOS 2.0

PhD - Leuven | More than two weeks ago

CMOS platform disintegration, combining new devices, sequential and backside processing is the future paradigm change in circuit design in sub-nm technology nodes.

Logic technology has continuously scaled proportional to minimum contacted gate pitch (CGP) and metal pitch (MP). Device performance scaling has been addressed by the introduction novel devices such as nanosheets and the integration alternate high mobility channels. Nonetheless, the single thread performance at the System on chip (SoC) level has plateaued and computer architecture solutions are being explored. However, process technology will continue to play a vital role in system scaling. Further dimensional scaling is believed to be enabled by 2.5D and 3D integration techniques, by deconstructing the SoC into multiple chiplets. Beyond dimensional scaling and DTCO, it is expected that further Application-Technology optimization and design can identify technology solutions to address issues like the memory wall, power distribution and partitioning of SoC sub-systems.

System 3D partitioning is already happening where the 3D-SoC is driven by heterogeneity and system level connectivity. The next potential future step is the CMOS disintegration down to the CMOS platform itself. The combination of new devices, sequential and backside processing allows for a Hybrid CMOS platform called CMOS 2.0 (Fig 1). The wafer backside can be exploited for functionality, signal routing and power distribution. Sequential processing can allow to split logic and cache memory at the fine interconnect pitch. Finally, novel devices, processed in the back-end-of-line allows to split short range high-density logic and high-performance logic for long range connectivity.

In this PhD we aim to change the paradigm of circuit design by exploiting the technology heterogeneity offered by CMOS 2.0. You will perform circuit and SoC level analysis to understand the fundamental power performance trade-off in current homogeneous technology SoCs. This understanding will allow to radically redesign the digital SoC for heterogeneous technology using various components of CMOS 2.0. You will work in a team of digital circuit designers and interact regularly with device process engineers and researchers that address various aspects of the CMOS 2.0 technology components.

Digital design and technology optimization using hybrid CMOS 2.0

Required background: Master in Electrical Engineering with CMOS design background preferably in the context of data path design and microarchitectures. Experience using EDA tools e.g. synthesis, static timing analysis or place and route is a plus


Type of work: 20% literature, 10% device technology, 10% circuit design, 50% design automation

Supervisor: Wim Dehaene

Co-supervisor: Pieter Weckx

Daily advisor: Giuliano Sisto

The reference code for this position is 2023-027. Mention this reference code on your application form.

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