Digital design for extreme device variability in sub 1nm technology nodes

Logic technology has continuously scaled proportional to minimum contacted gate pitch (CGP) and metal pitch (MP). Device performance scaling has been addressed by the introduction of vertically stacked lateral gate all around Nanosheet devices, which offer better electrostatic control over current FinFET devices. The ability to integrate alternate high mobility channels, such as SiGe and Ge and ultra-thin channels (<5nm thickness) provides a scaling path forward for improved performance. Finally, 2D materials such as MoS2, WS2 or HfS2 can be used to form atomic channel transistors, offering high mobilities and gate length scaling potential. As these transistor channel dimensions scale within the range of patterning and process resolutions, an increase intrinsic device performance variability becomes inevitable.

When designing a System-on-Chip (SoC) device performance variability needs to be addressed in order to meet timing margins, by approaches such as Static Timing Analysis (STA). This allows designers to qualify their design across many conditions by abstracting all possible condition into a number of critical design corners, which aim to span the entire design space. Under the presence of extreme variability, these approaches, however, result in sub-optimal designs preventing further SoC performance scaling for advanced nodes. Variability induced timing violation are the product of both combinational logic delay variation and clock skew and jitter. Therefore, critical path logic depth, buffer and drive strength sizing and clock tree design will have a distinct impact on how extreme device variability will define the SoC performance.

In this PhD we aim to change the paradigm of circuit design and design automation to enable digital design under extreme device variability. It will involve working with state-of-the art novel device compact models for ultra-thin and atomistic channel transistors. You will perform circuit and SoC level analysis to understand the critical variability bottlenecks for digital designs. Circuit design techniques to minimize timing violation will be addressed. These include careful design of the combinational logic and sequential logic standard cell families and variability aware clock tree design and optimization. Furthermore, on-chip mitigation approaches to handle extreme variability will be explored. These may include architectures that stall or flush the pipeline for timing failures, general latch-based design that use time borrowing, or self-healing resilient architectures with an error recovery mechanism.

You will work in a team of digital circuit designers and interact regularly with device engineers and researchers that address variability aspects.