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Disruptive research to complementary field-effect transistor (CFET) device integration for beyond 1nm logic technology nodes based on area-selective deposition (ASD) of dielectric insulation on metal surfaces.
Leuven | More than two weeks ago
In depth fundamental understanding of ALD of dielectric materials and surface chemistry to enable innovative and technologically relevant solutions for nano-electronic component miniaturization
As we approach the limits of scaling devices, novel device architectures are needed in order to meet the demand of a smaller transistor footprint while maintaining high performance and low power. For nodes beyond the 5nm regime, several options have been proposed. The most promising of these ideas include vertically stacked Nanosheets, Forksheets, and CFETs. The common theme in these approaches is to go from a horizontal to a vertical architecture. A CFET architecture, where NMOS and PMOS devices are vertically stacked and are controlled using a common gate, would result in maximum device footprint reduction.
Nevertheless, there are many challenges associated with the implementation of these novel architectures (see schematics), such as the thickness uniformity control of the dielectric insulation in the current approach based on dielectric etch back. Therefore, this PhD project is focused on the selective deposition of a Si dielectric insulation layer on metals such as Ru, W, Mo or Co by topographical deposition or surface-driven atomic layer deposition (ALD). Organic passivation of the Si nitride non-growth area will be studied in combination with low temperature ALD Si processes. A fundamental study of selectivity and defect formation mechanisms will be an important part of this PhD project together with the advanced characterization of precleaned surfaces, functionalized non-growth surfaces, both growth and non-growth surfaces exposed to gas phase reactants, deposited films, and formed defects.
The final goal of this project is to treasure all the learning gathered on un-patterned surfaces to nano-scale 3D features where the growth and selectivity mechanisms are expected to be different with respect to planar surfaces, due to different incoming surface composition (after etching and post-etching clean) and due to topography/geometry effects.
A great asset offered by Imec is the possibility of getting sub-20 nm patterned features as a result of cutting edge technology, integration and state-of-the-art materials and 300 mm IC manufacturing equipment.
A cross-team collaboration between the surface and interface preparation, thin film deposition and characterization experts will enable and in-depth understanding of material properties and mechanisms.
Type of project: Thesis
Duration: 12 months
Required degree: Master of Engineering Technology, Master of Engineering Science
Required background: Nanoscience & Nanotechnology, Materials Engineering, Chemistry/Chemical Engineering
Supervising scientist(s): For further information or for application, please contact: Silvia Armini (Silvia.Armini@imec.be)
Only for self-supporting students.