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/Distributed Computer Architecture Simulation: Checkpointing and Performance Optimization

Distributed Computer Architecture Simulation: Checkpointing and Performance Optimization

Leuven | More than two weeks ago

To help improve a simulation framework to model future compute system architectures.
​In simulating systems where long simulation-runtimes are a norm, a technique called checkpointing can be invaluable, wherein, a 'snapshot' of the simulation can be saved at time (t), and at a later point, the simulator is able to reload this snapshot and resume the simulation (t+1 onwards). A reference example of this can be seen in Gem5, a popular event-driven simulation framework for computer architecture research (see: gem5: Checkpoints).  

Structural Simulation Toolkit (SST) (sst-simulator.org) is a distributed event-driven simulation framework, also used for computer architecture research. There is some support for checkpointing in SST, but not complete. In this work, the objective is to enable and test checkpointing in SST.  Performance profiling and optimization of distributed simulation with SST framework could also be an interesting research component in the thesis (e.g., profiling and workload specific simulation partitioning). 

The prospective candidate needs to have strong C++ background, familiarity with parallel programming (e.g., MPI) is a plus. Familiarity with computer architecture research is good to have but not essential. 



Type of project: Thesis, Internship

Duration: 6 or 9 months

Required degree: Master of Engineering Science

Required background: Computer Science, Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Vinay Kumar Baapanapalli Yadaiah (Vinay.Kumar.BaapanapalliYadaiah@imec.be) and Sayandip De (Sayandip.De@imec.be)

Imec allowance will be provided.

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