/Efficient Algorithms for Speeding-Up Cell-Aware Test Library Characterization

Efficient Algorithms for Speeding-Up Cell-Aware Test Library Characterization

Master projects/internships - Leuven | More than two weeks ago

Cell-aware tests are better-quality tests for IC manufacturing defects; can you speed up their generation? 

Cell-aware test (CAT) is an automatic test pattern generation (ATPG)-based approach that targets defects within library cells. CAT offers a higher quality test compared to conventional ATPG methods, which can only detect cell-internal defects fortuitously. 
The CAT flow consists of two phases: library characterization and cell-aware ATPG. During library characterization, potential cell-internal defects are identified, and analog simulations are performed to determine which cell-level test patterns can detect which cell-internal defects. Cell-aware ATPG expands the cell-level test patterns to the chip level, while trying to maximize the coverage of the detectable cell-internal defects and to minimize the number of chip patterns. 
Characterization is performed only once per library, but in today’s implementations it is nevertheless a very time-consuming task, since it performs analog simulation on every library cell, for every potential cell-internal defect, and with every cell pattern. To accelerate the library characterization process, efficient algorithms based on structural analysis can be used to identify which cell-level test patterns need to be simulated for each cell-internal defect. By excluding the unnecessary analog simulations, a substantial reduction in overall characterization time can be achieved. 
Modern commercial cell libraries include many complex library cells, which results in a pressing need for both the high-quality test offered by CAT and for a time-efficient test generation flow. Within the scope of this thesis project, our primary objective is to develop and implement algorithms for efficient CAT library characterization of scaled commercial technology nodes.

Type of Project: Combination of internship and thesis 

Master's degree: Master of Engineering Science; Master of Engineering Technology; Master of Science 

Duration: 9 months 

Master program: Electrotechnics/Electrical Engineering; Computer Science 

Supervisor: Ingrid De Wolf

For more information or application, please contact Erik Jan Marinissen (erik.jan.marinissen@imec.be)


Imec allowance will be provided. 

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