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/Electro Static Discharges (ESD) impact on IC manufacturing process: improved procedure to reduce yield loss duiring die handling.

Electro Static Discharges (ESD) impact on IC manufacturing process: improved procedure to reduce yield loss duiring die handling.

Leuven | More than two weeks ago

ESD can generate issues on the fuctionality of Integrated Circuits (IC). These issues can seriously impact the overall chip functionality contributing to yield loss and product scrap. In this work we report what has been done to reduce ESD risks during die cleaning process

Type of project: Combination of internship and thesis

Required language: English

Required background: Electronics, Data analysis, Processing, IC, Matemathics, statistics

Mentor: Paolo Cerone

Manager: For more information or for application, please contact Antonio La Manna (Antonio.LaManna@imec.be)

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