/Energy efficient writing scheme for domain wall logic devices using voltage controlled magnetic anisotropy

Energy efficient writing scheme for domain wall logic devices using voltage controlled magnetic anisotropy

Leuven | More than two weeks ago

Exploring advanced spintronic devices for future computing architecture
Domain walls (DWs) are boundaries between two neighboring magnetic domains. The electrical manipulation of these boundaries in nanostructures could ultimately lead to the development of new computing systems to store and process information. DW logic devices are one of the potential candidates to circumvent the dimensional scaling issues of conventional CMOS devices. In a DW device, the logic information is encoded in a magnetic domain while current induced DW motion is employed to perform the logic operation [1].

 

   In principle, DW logic devices have three main components, each with its own specific functionality: DW writing (input), DW transport (in a circuit for logic operation) and DW reading (output). Therefore, in a DW logic device, the energy consumption not only depends on how fast current driven DW motion is in a logic circuit but also significantly depends on how the DW is written and read at the logic input and output, respectively. So far, research into DW physics has been most active in material development for faster and more efficient DW motion while the generation of DW in a logic device was rarely focused. At imec, we recently demonstrated that spin transfer torque (STT, i.e., the interface effect that allows the magnetic state in a magnetic tunnel junction to be switched by using spin polarized current) can be used as a writing scheme to generate DW in a nanoscale DW device [2]. However, the electrical current-based writing approach causes a large amount of power dissipation due to the Ohmic conduction. As a result, it leads to a high-power consumption due to Joule heating and particularly severely impacts on the reliability of nanoscale magnetic tunnel junction (MTJ) devices.

 

     This internship aims to circumvent this challenge by exploring a novel writing scheme of DW in a logic device using voltage controlled magnetic anisotropy (VCMA). The application of a gate voltage across the MTJ will reduce or remove the energy barrier inducing a magnetization switching [3]. This effect has been experimentally demonstrated as an energy efficient writing scheme of MTJs in MRAM technology [3]. However, the use of VCMA effect for electrical generation of DWs in a logic device is still missing. By mean of micromagnetic simulation (OOMMF, MuMax, etc.), the student will explore the effect of VCMA on the generation of DWs at the MTJ inputs in a DW logic devices. The student will study the dynamical modification of an energy barrier during DW writing operation. The study will then focus on analyzing the shape of domain and energy consumption of VCMA-based approach compared to STT-based approach. This obtained result will ultimately guide and support for experimental realization towards low power DW logic devices.  

  

1. Luo, et al. Current-driven magnetic domain-wall logic. Nature 579, 214–218 (2020).

2. Raymenants et al., Nanoscale domain wall devices with magnetic tunnel junction read and write, Nat. Elec. 4, 392 (2021).

3. Nozaki et al., “Recent Progress in the Voltage-Controlled Magnetic Anisotropy Effect and the Challenges Faced in Developing Voltage-Torque MRAM” Micromachines 10, 327 (2019)

Type of project: Combination of internship and thesis

Required degree: Master of Engineering Technology, Master of Science

Required background: Physics, Materials Engineering

Supervising scientist(s): For further information or for application, please contact: Van Dai Nguyen (Van.Dai.Nguyen@imec.be) and Maxwel Gama Monteiro (Maxwel.GamaMonteiro@imec.be)