Epitaxial SiGe source/drain growth studies on different Si surfaces in view of nanosheet devices

Leuven
|
More than two weeks ago

The new devices for advanced technological nodes set special challenges on the conditions used for the epitaxy of the Source/Drain (S/D) contact layers which will be investigated during this work.

Nanosheet and nanowire‐based MOSFET devices (also called Gate‐All‐Around or GAA MOSFET) provide an optimal electrostatic control of carriers in the channel. They are expected to extend transistor scaling beyond the FinFET limits. GAA designs take advantage of a process flow relatively comparable to that of FinFETs. Vertical stacking of GAA channels allows to maximize the drive current for a given footprint on the wafer. However, these devices do not provide benefits in scaling the cell height. As an alternative,novel vertically stacked lateral nanosheet devices such as Complementary FET (CFETs) have been proposed. The new devices set special challenges on the conditions used for the epitaxy of the Source/Drain (S/D) contact layers. The S/D must be initiated on the nanosheet sidewalls. The growth then proceeds laterally instead of the common vertical [001] direction, which modifies the growth behaviors and the final layer properties.

Imec reported breakthroughs in the low temperature epitaxy of various SiGe materials. The epilayers are grown by Reduced‐Pressure Chemical Vapor Deposition (RP‐CVD) with novel Si and Ge precursors. This enables far‐from‐thermodynamic‐equilibrium epitaxial growth, leading to higher active S/D doping concentrations at reduced thermal budgets. High levels of active doping are needed to reduce the contact resistance to the devices and improve their performance. In the current project, the candidate will study differences in epitaxial growth behaviors linked to modified device architectures. The orientation of the starting surface affects the growth rate, the final material composition and doping concentration. A special mask is available for this assessment. The final process evaluation will be done on real device structures with scaled dimensions.​


Type of project: Thesis, Combination of internship and thesis

Duration: 6 month

Required degree: Master of Science, Master of Engineering Science, Master of Engineering Technology

Required background: Materials Engineering, Physics, Nanoscience & Nanotechnology, Chemistry/Chemical Engineering

Supervising scientist(s): For further information or for application, please contact: Andriy Hikavyy (Andriy.Hikavyy@imec.be) and Roger Loo (Roger.Loo@imec.be) and Clement Porret (Clement.Porret@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.

Share this on

truetrue

This website uses cookies for analytics purposes only without any commercial intent. Find out more here. Our privacy statement can be found here. Some content (videos, iframes, forms,...) on this website will only appear when you have accepted the cookies.

Accept cookies