PhD - Leuven | More than two weeks ago
ESD reliability is essential to enable future Optical Interconnects
Optical I/O (OIO) interfaces using Silicon or Group IV based photonic components are a promising and upcoming cost-efficient technology for low power and high bandwidth optical links between CMOS ICs at the chip-to-chip or board-to-board level . These OIO interfaces enable data transfer from the electrical domain to the optical domain, and then back to the electrical domain. For the Si-photonics studied here, at the optical transmitter (TX) end, an external laser beam is modulated by Si or Ge modulators and is then transmitted via Si waveguides in the Silicon-On-Insulator (SOI) optical interposer. At the receiver (RX) end, the optical signal is converted into an electrical signal using Ge photodetectors. Figure 1 illustrates this integration of the optical components with the optical interposer [1, 2]. As for other 2.5D interposer integrations, all the optical components are exposed to electrostatic discharge (ESD) threats during the assembly . Limited prior works have disclosed the corresponding ESD protections of the Si-photonic components in optical interposers . ESD protections account for a significant part of the parasitic loads. Appropriate ESD mitigation strategies which include both design of integrated ESD protection circuits and ESD prevention in the manufacturing environment, are key factors for designing high-speed I/O interfaces, especially for the internal OIO interfaces that connect the stacked dies on optical interposers.
Recently, a n-III-V/p-Si heterojunction has been proposed as a new carrier depletion-type hybrid III-V/Si optical phase shifter . III-V compound semiconductors possess superior material properties which are beneficial to optical phase modulating applications [5-8]. Several publications have presented the feasibility of III-V/Si hybrid integration for the optical phase shifters, but the corresponding III-V/Si bonding process steps and the follow-up III-V contact metallization significantly increase the manufacturing complexities and challenges in current CMOS technologies. In , the III-V/Si heterojunction is fabricated with direct epitaxial growth of III-V semiconductors on SOI substrates. This proposed III-V/Si epitaxial technology option can mitigate process complexities and may enhance the further integration and implementation in mature CMOS facilities . However, ESD has been often considered as one of the main reliability concerns in III-V compound semiconductors . The ESD characteristics of n-III-V/p-Si heterojunction have not yet been investigated so far.In this doctoral program, fundamental ESD transient characteristics of the Si (or GeSi) optical components will be firstly studied and corresponding ESD protection options in the state-of-the-art optical interposer technologies will be further evaluated and analyzed. Next to Group IV based photonic components, the ESD challenges in emerging n-III-V/p-Si heterojunction technologies will be explored to comprehend the related failure mechanisms and to propose proper ESD protection solutions in these novel III-V photonic components.
Required background: Master degree in Electronic Engineering, Materials Science and Engineering, or Physics. Preferred: Semiconductor Device Physics, VLSI Design and Process/Integration, Solid-State Physics, Layout/SPICE Design Environment
Type of work: literature (10%), advanced photonic technology study (20%), test structure design and layout (20%), experimental measurement (30%), and TCAD device simulations (20%)
Supervisor: Piet Wambacq
Co-supervisor: Bertrand Parvais
Daily advisor: Shih-Hung Chen
The reference code for this position is 2022-038. Mention this reference code on your application form.