Research & development - Leuven | More than two weeks ago
Evaluating Digital Inference Engine for suitability in High-Performance Heterogenous Inference Accelerator
With the massive growth in size of neural networks, energy consumption of neural network inference has also risen. From a computation perspective, quantization techniques are used widely for lowering computational complexity. From the hardware perspective, analog-in-memory computing (AiMC) based solutions have grown popular in recent years. AiMC based compute cells which store the neural network weights, natively support very low precisions (often binary or ternary). AiMC based solutions have extremely high energy efficiency of the order of 1000Tops/W.
Digital inference engines offer higher flexibility of operations and high precision. From the algorithmic perspective, layers in the neural network that require higher precision can be mapped to the digital inference engine. Also, digital inference engines allow efficient processing of sparse neural network layers. These factors make it interesting to have digital and analog inference engines together in a high-performance inference accelerator.
The specific goals of this project are as follows:
Mandatory: Computer Architecture, RTL (Verilog preferred), C++, familiarity with deep neural networks.
Optional: Python, Pytorch, Familiarity with EDA tools
Type of project: Thesis
Duration: upto 6 months
Required degree: Master of Engineering Technology, Master of Science, Master of Engineering Science
Required background: Electrotechnics/Electrical Engineering, Computer Science
Supervising scientist(s): For further information or for application, please contact: Debjyoti Bhattacharjee (Debjyoti.Bhattacharjee@imec.be) and Peter Debacker (Peter.Debacker@imec.be) and Arindam Mallik (Arindam.Mallik@imec.be)
Imec allowance will be provided for students studying at a non-Belgian university.