Experimental characterization of selector for high-density memory

Leuven - Master projects
About a week ago

Hands-on experience on solutions for industry's high density memory challenges

These last years, the demand for high-density and fast-access non-volatile memories has been steadily increasing. However, there is no existing product satisfying this need today, between the fast but volatile DRAM technology and the high-density but slow-access 3D Flash technology. Hence, the ‘Storage Class Memory’ (SCM) has emerged to fill this speed-density gap in the memory hierarchy, enabling the development of future computing and/or storage systems by providing a fast and cheap memory alternative.  


Several emerging memory concepts, like resistive random-access-memory (RRAM), phase-change RAM (PCRAM), or Magnetic RAM (MRAM) concepts hold the promise of showing both speed and density specifications of SCM. On the other hand, in today’s memory array cross-point architecture, the main factor limiting high-density integration is the “sneak path” current or capacitive issue during read and write programming of the memory device. To overcome this issue a two-terminal access device (selector) in series with the memory element is required to enable addressing individual memory cells in an array without disturbing the others. This select device must be scalable, have high rectification ability, following the operation mode of the memory cell (typically bipolar) and allow for high drive current densities, required to switch the memory element.  


To fulfill these requirements, many selector concepts are currently under investigation. Amongthem, imec has recently advanced in the development of the chalcogenide-based Ovonic Threshold Switch (OTS) technology. For high enough voltages, OTS technology relies on the appearance of a negative differential resistance (NDR) branch in the selector I-V characteristic to grand high driving capability and large non-linearity. These performances come at the expense of relatively high voltage and voltage spiking across the memory element. Although excellent potential was demonstrated for this technology [1,2], the switch mechanism is not well understood. Alternative selector concepts, generally based on the rectifying behavior of Schottky contact, are also investigated in view of close integration with MRAM technology. Indeed, such selectors, characterized by a diode-like behavior, generally avoid OTS voltage issue which is critical for a low voltage, low power technology such MRAM. Imec has recently started a broad research activity on the topic exploring Mixed Ionic Electronic Conductors (MIEC), Metal-Semiconductor-Metal (MSM) diode, novel vertical IGZO-based diode. 


The purpose of this MSc is to investigate the electrical performances and reliability properties of the above-mentioned selector devices by studying how composition, material variations, and integration processes, impacts critical device parameters in order to identify knobs for device improvement. To fulfill these goals state-of-the art measurement tools and data analysis software will be adopted. The MSc work will be carried out in the frame of the Imec Industrial Affiliation Program (IIAP), thus in close relation with industrial partners and within a team consisting of experts in various fields (processing, integration, physical characterization, modeling, reliability...). ​


References: [1] B. Govoreanu et al., VLSI 2017, [2] S. Clima et al., IEDM 2017.​​


Type of work: Experimental work (electrical characterization (70%)), and simulation and modeling (~10%), up-to-date literature on selectors (~20%)

Type of project: Combination of internship and thesis

Duration: 6-9 Months

Required degree: Master of Science

Required background: Nanoscience & Nanotechnology

Supervising scientist(s): For further information or for application, please contact: Andrea Fantini (Andrea.Fantini@imec.be) and Daniele Garbin (Daniele.Garbin@imec.be)

Imec allowance will be provided

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