PhD - Leuven | More than two weeks ago
As the demand for faster, smaller, and more power-efficient devices is increasing, conventional memories such as SRAM and DRAM are reaching their scaling limits. Recently, STT-MRAM (spin transfer torque magnetic random-access memory) has been successfully introduced as a compelling candidate for on-chip memory applications. This first success calls for further explorations of other spintronics concepts. Alternative switching mechanism such as spin orbit torque (SOT) or voltage control of magnetic anisotropy (VCMA) are already actively researched to enable new applications of MRAMs. While traditional MRAM rely on individual junctions to address a single magnetic bit, new concepts are emerging that aims to move magnetic bits from one pillar to the next via domain-wall transport. This concept promises to increase further the memory density while enabling high throughput for high-bandwidth applications such as machine learning.
State-of-the-art and challenges
A domain-wall based memory device is composed of magnetic tunnel junctions (MTJ) as input/output which are interconnected through a magnetic track. Domain walls are nucleated (either by STT, SOT or even VCMA) under a pillar and are then pushed towards the output by an applied current. While the basic concept is relatively simple, most of the research on domain wall propagation has been done on relatively large structures and without MTJ integration. At Imec, we want to tackle the challenges related to this concept in strongly scaled device. What are suitable materials for high domain wall speed? What can be used as reliable mechanism to move and fix the wall in a specific place? What device concept is most practical?
In addition to the memory applications, there is currently a strong interest in DW-based concepts for machine learning. This mostly because they enable in a relatively simple way to implement an analog in-memory computing.
Experimental details & Methodology
Imec is developing the basic building blocks of this DW device for memory and machine learning. The devices are fabricated on 300mm wafers in its state-of-the-art cleanroom. During this PhD, you will take part in the characterization of these new types of devices. This means performing electrical measurement on a 300mm (magnetic) prober but also developing your own measurement scheme and routine specifically needed for the domain wall device analysis. The end-goal is to investigate the physics governing the functionality of the device. As such it is also expected that you will guide the design of the next generation devices that would exploit domain-wall physics. It is expected that the electrical measurements will be complemented by micromagnetic simulation, necessary to comprehend the dynamics of these devices and their limitations.
Key to the Ph.D research is to:
Required background: Physics, electrical engineering
Type of work: literature study (10%), experimental work (70%), modelling (20%)
Supervisor: Kristiaan Temst
Co-supervisor: Claudia Fleischmann
Daily advisor: Siddharth Rao, Sebastien Couet
The reference code for this position is 2021-021. Mention this reference code on your application form.