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/Job opportunities/Exploring magnetic domain-wall based devices for memory and machine learning applications

Exploring magnetic domain-wall based devices for memory and machine learning applications

PhD - Leuven | More than two weeks ago

Expand the magnetic domain and application space for next generation devices

Background

As the demand for faster, smaller, and more power-efficient devices is increasing, conventional memories such as SRAM and DRAM are reaching their scaling limits. Recently, STT-MRAM (spin transfer torque magnetic random-access memory) has been successfully introduced as a compelling candidate for on-chip memory applications. This first success calls for further explorations of other spintronics concepts. Alternative switching mechanism such as spin orbit torque (SOT) or voltage control of magnetic anisotropy (VCMA) are already actively researched to enable new applications of MRAMs. While traditional MRAM rely on individual junctions to address a single magnetic bit, new concepts are emerging that aims to move magnetic bits from one pillar to the next via domain-wall transport. This concept promises to increase further the memory density while enabling high throughput for high-bandwidth applications such as machine learning.

State-of-the-art and challenges

A domain-wall based memory device is composed of magnetic tunnel junctions (MTJ) as input/output which are interconnected through a magnetic track. Domain walls are nucleated (either by STT, SOT or even VCMA) under a pillar and are then pushed towards the output by an applied current. While the basic concept is relatively simple, most of the research on domain wall propagation has been done on relatively large structures and without MTJ integration. At Imec, we want to tackle the challenges related to this concept in strongly scaled device. What are suitable materials for high domain wall speed? What can be used as reliable mechanism to move and fix the wall in a specific place? What device concept is most practical?

In addition to the memory applications, there is currently a strong interest in DW-based concepts for machine learning. This mostly because they enable in a relatively simple way to implement an analog in-memory computing.

 

Experimental details & Methodology

 

Imec is developing the basic building blocks of this DW device for memory and machine learning. The devices are fabricated on 300mm wafers in its state-of-the-art cleanroom. During this PhD, you will take part in the characterization of these new types of devices. This means performing electrical measurement on a 300mm (magnetic) prober but also developing your own measurement scheme and routine specifically needed for the domain wall device analysis. The end-goal is to investigate the physics governing the functionality of the device. As such it is also expected that you will guide the design of the next generation devices that would exploit domain-wall physics. It is expected that the electrical measurements will be complemented by micromagnetic simulation, necessary to comprehend the dynamics of these devices and their limitations.

 

Key to the Ph.D research is to:

 

  1. Study the physics of domain wall propagation in next generation magnetic domain wall devices
  2. Study of material for domain wall transport in dedicated test structures (hallbars)
  3. In-depth electrical characterization of fully integrated device
  4. Development of DW specific measurements schemes
  5. Perform micromagnetic simulations to support your observations
  6. You will be part of a collective effort: strong interaction with the thin film (material) group and other device characterization members is expected

     

    In a first phase, the student will perform an extensive literature search on the physics of domain wall transport, STT and SOT-driven dynamics and the different device concepts based on domain wall transport. A large part of the PhD will be focused on the electrical characterization of fully integrated domain wall devices where emphasize will be put on understanding the potential failure modes, identifying the showstoppers, and establishing a relationship to the materials used and the device integration. In support of this, it is expected that the student will also take part in studying domain wall transport in simplified devices, to identify the impact of material on transport. In parallel, micromagnetic modeling (OOMMF, mumax) will be performed to inform the electrical behavior of the device and guide the potential geometry and material to be used. Finally, the in-depth knowledge will be used to guide the development of the next iteration of devices and define what are the remaining key challenges of this technology.


Required background: Physics, electrical engineering

Type of work: literature study (10%), experimental work (70%), modelling (20%)

Supervisor: Kristiaan Temst

Co-supervisor: Claudia Fleischmann

Daily advisor: Siddharth Rao, Sebastien Couet

The reference code for this position is 2021-021. Mention this reference code on your application form.

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