Frequency synthesis for wireless communication beyond 100 Gbit/s

Leuven - PhD
More than two weeks ago

Millimeter-wave IC design in silicon technologies for wireless communication operating beyond 100 GHz


Wireless communication is continuously demanding for higher data rates. For example, end users with their mobile devices (smart phone, tablet, ...) are seeking for ever increasing resolutions of video that is streamed over the air. To enable all this, a massive amount of data must be transported in the backbone of the network. In this backbone,  communication not only happens via wires (copper, optical fibres) but also over the air.  Wireless datarates that are needed there exceed 100 Gbit/s. This requires large bandwidths, which are only available at frequencies beyond 100 GHz. More recent wireless applications that require ultra-high datarates are augmented reality and virtual reality. These are indoor applications, requiring shorter communication distances.‚Äč

Today, transceivers for wireless communication above 100GHz use III-V technologies (GaAs, InP, ...), which are quite expensive. This PhD work targets the design of wireless transceivers operating around 150 GHz based on silicon technologies. At these frequencies, a large bandwidth is available for wireless communication. However, the high operating frequency is challenging for silicon IC technologies. Some PhD work has already started for the implementation of the mm-wave building blocks in the signal path such as power amplifiers and low-noise amplifiers. This new PhD focuses on the design of the local oscillator (LO). The LO signal is used for upconversion and downconversion of signals in the transmit and receive path, respectively. The spectral purity of the LO signal is an important specification: a high spectral purity, corresponding to low phase noise and small spurious signals, enables complex modulation schemes that allow for a link with more bits per symbol than simple modulations.

Classically, the LO of a wireless transceiver is made with a phase-locked loop (PLL). This is a control system built around a voltage-controlled oscillator (VCO) whose frequency is kept fixed with the use of a stable reference signal coming from a spectrally pure crystal oscillator. Designing a low phase noise VCO at mm-wave frequencies is challenging. Alternatively, a lower frequency VCO can be designed which injection-locks a high-frequency oscillator.

The goal of this PhD is to develop an architecture for the LO and to implement it in a silicon-based technology. As a PhD. student you will team up with imec payroll people and other PhD students. Your LO will be combined with the RF section of a transmitter and receiver that will be completed by other PhD students. 

Required background: Master in Electrical Engineering, analog IC design experience

Type of work: 10% literature, 20% architecture design, 70% IC design including measurements

Supervisor: Piet Wambacq, Gerd Vandersteen

Daily advisor: Giovanni Mangraviti

The reference code for this position is 1812-61. Mention this reference code on your application form.


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