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/Job opportunities/From physics-based FET degradation models to circuit-level simulations

From physics-based FET degradation models to circuit-level simulations

PhD - Leuven | More than two weeks ago

Enabling circuit simulations with physics-based device degradation models to maximize technology lifetime

Several directions have been pursued by the semiconductor industry in the past decade.  In Field Effect Transistors (FETs), i) conventional Si and SiO2 are being replaced by more exotic materials, from high-k gate dielectrics to metal gates and to high-mobility substrates, ii)  new transistor architectures are being introduced, ranging from FinFETs to nanowire and nanosheet FETs,  iii)  transistors are downscaled toward atomic dimensions with each stochastically-behaving gate oxide defect potentially having a substantial impact on the device operation, while  iv) supply voltages are reduced; nonetheless, the electric fields are increasing.

All of these developments constitute new challenges for ensuring sufficient reliability, i.e., limited degradation during operation, of the FETs based on such advanced CMOS VLSI technologies.  Thorough, physics-based models are already being developed for the various degradation mechanisms (such as Bias Temperature Instability, Hot Carrier Degradation, etc.) occurring in different regions of the FET {Vgate, Vdrain} operating space.  These mechanisms include charging of preexisting defects in the gate dielectrics and simultaneous generation of new defects, e.g. by hot carriers, compounded by significant channel temperature increases due to FET "self-heating".

However, to understand the impact of the degradation on circuits, the existing physical insights need to be converted to compact models usable in SPICE-level simulations.  The Thesis work therefore encompasses: i) converting the already-developed physical models into such reliability-aware compact models able to describe the degradation (both mean and variation) of all major FET parameters, such as Vth, gm, SS, Id,lin, Id,sat, etc, in the entire {Vgate, Vdrain} operating space as a function of an arbitrary stress history, ii) enabling the simulation of FET degradation in various analog and digital circuits and understanding the implications for various circuit parameters, and iii) design, layout, and measurement of test circuits to validate the developed compact models and the simulation methodology.​

Required background: Msc in electronics or equivalent. Knowledge in: semiconductor device physics, transistor-level circuit simulations, transistor-level circuit design, layout, and electrical measurements

Type of work: 40% compact model development, 30% modeling and simulations, 30% methodology validation

Supervisor: Georges Gielen

Daily advisor: Ben Kaczer, Bertrand Parvais

The reference code for this position is 2020-049. Mention this reference code on your application form.
Chinese nationals who wish to apply for the CSC scholarship, should use the following code when applying for this topic: CSC2020-18.