/Heterogeneous High-Speed ADCs for 6G communications

Heterogeneous High-Speed ADCs for 6G communications

PhD - Leuven | More than two weeks ago

Design of >10GS/s data converters for Gbps wireless connectivity

Emerging communication standards such as 6G target bandwidths exceeding 10 Gbit/s and will revolutionize the fields of sensing, artificial intelligence (AI), augmented and virtual reality (AR/VR), and remote healthcare among others. The ultra-high wireless data rates offered by these technologies require Analog-to-Digital Converters (ADCs) operating at high sampling rate (>10 GS/s), high effective accuracy (>8b) and high linearity.


In essence, the design challenge of such an ADC lies within build-up of 1) linear/highly accurate RF front-end sampling and 2) energy efficient, high-speed back-end conversion. Traditionally, an ADC is a plain vanilla CMOS system, where different architectures clearly benefit from the “ride on the Moore’s law wave”. Core transistor’s performance shortcoming are successfully bypassed by clever analog and digital signal processing techniques. However, in context of the proposed specification space, this is no longer possible at a reasonable power cost. Despite the immense DSP power of deeply scaled nanometer CMOS, core analog performance of a transistor fails to satisfy the high-speed front-end sampler accuracy/linearity requirements.


The goal of this PhD is to investigate and implement routes for realization of ADCs with sampling rates >10 GSs/s and high accuracy/linearity levels (>8b), considering the limitations of current semiconductor processes. This will include investigation of heterogeneous implementations combining CMOS with III-V materials, where III-V can serve for build-up of RF front-ends, operating at unprecedented performance levels. With this in mind, at imec, we have been developing III-V devices on Si platform with innovative integration technologies. As a PhD researcher, you will be working on design and experimental realization of advanced vertical III-V devices targeting ADC front-end applications. You will work at the intersection of material science, semiconductor physics, and circuit design acquiring unique skillset to make impact in this vibrant research field.


Simultaneously, modern, deeply scaled CMOS can be exploited for efficient design of digitally intensive back-end. Numerous architectures are possible and must be considered. E.g. time-interleaved SAR ADCs typically are the best candidates for low power consumption, but because of their low intrinsic speed high interleaving factors are needed, leading to significant front-end loading issues. On the other hand, high-speed channels such as those built out of pipeline ADCs achieve higher speeds and need less time interleaving, but must be optimized to reduce power consumption. And many other topologies exist, each of them impacted by the specific CMOS technology node used. Obviously, the PhD also includes the actual circuit-level implementation of both the critical blocks as well as the whole ADC in several tapeouts. This must be done extremely rigorously, extracting all parasitic effects of the layout, and adapting the design until the target performance is achieved. All fabricated chips will be characterized using the high-speed measurement infrastructure available at imec.


This PhD takes place in the imec team of Jan Craninckx and Piet Wambacq, one of the world-leading groups in the area of high-performance RF, millimeter-wave and ADC design, with a strong publication record in the major conferences and journals of the solid-state circuits community.  This is a challenging PhD topic, requiring a highly motivated PhD student with strong interest to develop design skills in advanced CMOS nodes.

Required background: analog IC design

Type of work: 10% literature, 30% device modeling/characterization, 40% simulation & layout, 20% measurements

Supervisor: Piet Wambacq

Co-supervisor: Jan Craninckx

Daily advisor: Nereo Markulic

The reference code for this position is 2023-071. Mention this reference code on your application form.

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