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/Job opportunities/High-level area and power estimation modeling for hardware algorithm

High-level area and power estimation modeling for hardware algorithm

Research & development - Leuven | More than two weeks ago

Enabling closed-loop brain computer interfaces

To compress the transmission data and enable closed-loop recording and stimulating experiments, efficient hardware spike sorting is highly desirable for next-generation neural probes. For this purpose, a variety of spike sorting algorithms have been developed from a software perspective, mainly focusing on processing accuracy. However, in addition to accuracy, silicon area and power consumption are also essential for efficient hardware realization. Thus, to close the gap between software and hardware design, it becomes critical to accurately estimate the area and power overheads for algorithms at high level.


The goal of this internship is to analyze and model the computational complexity and memory requirements of spike sorting algorithms in hardware implementation. Eventually, the student will develop a methodology to assess the silicon area and power consumption with a specific technology. The intern student will be involved in the analysis of algorithms, digital system architecture, and RTL design and synthesis.


Specific internship objectives:

  • Study and understand the theory behind neural recording and spike sorting.
  • Analyze the number of elementary arithmetic logic operations and memory read/write operations for different spike sorting algorithms.
  • Create models to estimate the gate counts and memory requirements based on the analysis of algorithms.
  • Create models to estimate the area and power of different algorithms for specific technology nodes.
  • Develop a methodology to implement the area and power estimation merely based on algorithm analysis.
  • Validate the methodology through RTL design and synthesis.



  • Interest and enthusiasm in signal processing and algorithms
  • Knowledge of Python or Matlab
  • Knowledge of Verilog or VHDL
  • Knowledge of digital IC design principles
  • Knowledge of computer architecture or AI architecture is a plus

Type of project: Internship

Duration: 6-9 months

Required degree: Master of Engineering Science, Master of Engineering Technology

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Yingping Chen (

Imec allowance will be provided for students studying at a non-Belgian university.