Research & development - Leuven | More than two weeks ago
To compress the transmission data and enable closed-loop recording and stimulating experiments, efficient hardware spike sorting is highly desirable for next-generation neural probes. For this purpose, a variety of spike sorting algorithms have been developed from a software perspective, mainly focusing on processing accuracy. However, in addition to accuracy, silicon area and power consumption are also essential for efficient hardware realization. Thus, to close the gap between software and hardware design, it becomes critical to accurately estimate the area and power overheads for algorithms at high level.
The goal of this internship is to analyze and model the computational complexity and memory requirements of spike sorting algorithms in hardware implementation. Eventually, the student will develop a methodology to assess the silicon area and power consumption with a specific technology. The intern student will be involved in the analysis of algorithms, digital system architecture, and RTL design and synthesis.
Specific internship objectives:
Type of project: Internship
Duration: 6-9 months
Required degree: Master of Engineering Science, Master of Engineering Technology
Required background: Electrotechnics/Electrical Engineering
Supervising scientist(s): For further information or for application, please contact: Yingping Chen (Yingping.Chen@imec.be)
Imec allowance will be provided for students studying at a non-Belgian university.