High-Speed ADCs for Next-Generation Optical Links

Popular cloud-based software applications such as video-on-demand, internet search engines, streaming, social media all rely on warehouse scale data centers. These house tens of thousands of computing nodes, all interconnected via high capacity optical links. Optical transceivers for these links currently have 100Gb/s to 400Gb/s capacities, achieved through multiplexing multiple lanes, e.g. 4 lanes running at >50Gbaud (100Gb/s) PAM-4. Data center operators foresee a need for 800Gb/s and even 1.6Terabit/s optical links within the next 5 to 10 years, which will need an increase in signaling rate on these links up to at least 100Gbaud.

A critical component for state-of-the-art optical transceivers is a high sampling rate (>>100GS/s) analog-to-digital converter (ADC). Such ADC allows implementation of advanced digital signaling processing (DSP) algorithms (equalization, forward error correction, …) to recover the transmitted bits from signals that will be severely distorted due to e.g. limited bandwidth of front-end electronics, optical modulators and detectors, chromatic dispersion introduced by the optical fiber etc. The use of ADCs (sampling at twice the baudrate) and DSP is now widespread for e.g. coherent optical links, as well as PAM-4 optical links, operating up till ~56Gbaud.

At transmission rates up to and beyond 100Gbaud, no solutions today exist to realize sufficiently fast ADCs. CMOS scaling down to 7 or 5nm has increased DSP power significantly, but the speed of CMOS transistors no longer scales with technology nodes as fast as it used to, riding the wave of Moore's law does not work anymore. This enormous challenge calls for fundamental research into new architecture and technology options for optical receiver ADCs.

The goal of this PhD is to investigate and implement routes for realization of ADCs with sampling rates well in excess of 100GS/s. In a first phase, taking into account the limitations of current semiconductor processes, the ADC architecture will be defined. This will include e.g. hybrid implementations combining CMOS with SiGe BiCMOS processes, digital compensation techniques, ultra-fast ADC architectures, etc. The second step of the PhD consists of the actual circuit-level implementation of both the critical blocks as well as the whole ADC in one or more tapeouts, which then in a final step can be characterized using the high-speed measurement available at imec.

This PhD takes place in the imec team of Jan Craninckx and Piet Wambacq, one of the world-leading groups in the area of high-performance RF, millimeter-wave and ADC design, with a strong publication record in the major conferences and journals of the solid-state circuits community.  We also collaborate with the team of Johan Bauwelinck and Peter Ossieur, who have an internationally recognized track record in the area of high-speed optical transceiver design. Both groups are looking to combine their knowledge on high-performance ADC design on one hand and high-speed transceiver realizations on the other hand to create the next generation of >100Gbaud capable optical links.

This is a challenging PhD topic, requiring a highly motivated PhD student with strong interest to develop design skills in advanced CMOS nodes.