/High-speed Time-domain ADCs for Next-generation Wireline Communications

High-speed Time-domain ADCs for Next-generation Wireline Communications

PhD - Leuven | More than two weeks ago

Design >>100GS/s analog-to-digital converters for the future internet

Popular cloud-based applications such as video-on-demand, internet search engines, streaming, and social media rely all on warehouse-scale data centers, which comprise tens of thousands of computing nodes interconnected via high-capacity optical links. Optical transceivers for these links currently feature data rates in the 100Gb/s to 400Gb/s range, which are achieved by the multiplexation of several lanes, e.g. 4 lanes of PAM-4-modulated data at >50Gbaud (100Gb/s) per lane. Data center operators foresee the need for 800Gb/s and even 1.6Tbit/s optical links within the next 5 to 10 years, calling for an increase in the lane data rate to at least 100Gbaud.


A critical component in state-of-the-art optical transceivers is an analog-to-digital converter (ADC) with moderate resolution and very high sampling rate (>>100GS/s). Such ADC allows the implementation of advanced digital signaling processing (DSP) algorithms for equalization, detection and error correction, which are required to recover the transmitted data from signals that are heavily distorted due to various impairments, including limited bandwidth of front-end electronics, optical modulators and detectors; chromatic dispersion in the optical channel, etc. The combined use of ADCs and DSP is now widespread for e.g. PAM-4 optical links operating up to 56Gbaud, requiring time-interleaved ADCs with >100GS/s of aggregate sampling rate and resolutions of 5 to 6 effective number of bits (ENOB).


For the future optical links, however, higher data rates and more spectrally-efficient modulation schemes like PAM-6 or PAM-8 will be required, raising the ADC sampling rate and resolution requirements to >>100GS/s and 7 to 8 ENOB, respectively. While CMOS scaling in deep-nanoscale nodes has increased the capabilities of DSP significantly, it has severely compromised the performance of traditional moderate-resolution wideband ADCs. In fact, at transmission rates up to and beyond 100Gbaud, no solutions today exist for the realization of sufficiently-fast ADCs at the required ENOB levels. This enormous challenge calls for fundamental research into new architectures and circuits for next-generation optical-receiver ADCs.


A recent approach for the realization of high-speed, moderate resolution analog-to-digital conversion is the use of time-domain ADCs. These converters exploit the fact that as digital nodes scale down they become faster, allowing digital circuits to achieve better resolution in the time domain. This is in stark contrast with what happens to traditional voltage-domain ADCs, where the resolution in the voltage domain is degraded by the ever-decreasing supply voltages of deeply scaled nodes. Thus, unlike traditional voltage-domain ADCs, time-domain ADCs greatly benefit from process scaling, allowing them to achieve single-channel conversion speeds of several GS/s at moderate resolutions in nanoscale CMOS. Moreover, their highly-digital nature allows them to achieve comparatively small silicon footprints. As a result, time-domain ADCs constitute an ideal candidate for the realization of time-interleaved converters achieving >>100GS/s of aggregate sampling rate, yet with reduced interleaving factors and area.


The goal of this PhD is to investigate and implement routes for the realization of moderate-resolution ADCs with sampling rates well in excess of 100GS/s. In a first phase, the ADC architecture will be defined, leveraging time-domain analog-to-digital conversion and time-interleaving techniques. The second step of the PhD consists in the actual circuit-level implementation of both the critical blocks as well as the whole ADC in one or more chip tapeouts, which in a final step will then be characterized using the high-speed measurement infrastructure available at imec.


This PhD takes place in the imec team of Jan Craninckx and Piet Wambacq, one of the world-leading groups in the areas of high-performance RF, millimeter-wave, and ADC design, with a strong publication record in the major conferences and journals of the solid-state circuits community. This is a challenging PhD topic, requiring a highly motivated PhD student with strong interest in developing design skills in advanced CMOS nodes.


Required background: Experience in analog IC design

Type of work: 10% literature; 70% design, simulation & layout; 20% measurements

Supervisor: Piet Wambacq

Co-supervisor: Jan Craninckx

Daily advisor: Jorge Lagos Benites

The reference code for this position is 2024-077. Mention this reference code on your application form.

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