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Impact of Inspections and Metrology steps on the Turn Around Time (TAT) for wafer processing in a semicondutor R&D Fab.
Leuven | More than two weeks ago
The manufacturing of a semiconductor device is based on several processing steps that are implements on Si-based wafers. In an R&D environment, these processing steps are not always pre-defined and requires multiple inspections along the processing. This work has the objective to quantify the differences between a standard wafer processing and and R&D wafer processing
Type of project: Combination of internship and thesis
Required language: English
Required background: Electronics, Data analysis, Processing, IC, Matemathics, statistics
Mentor: Massimiliano Maranella
Manager: For more information or for application, please contact Antonio La Manna (Antonio.LaManna@imec.be)