The emergence of nonvolatile memories, data driven application domains and machine intelligence has triggered a massive rethinking of the design protocols and algorithms that governed System on Chip (SoC) devlopment. The inevitable evolution towards rich, chip-level integration for diverse application domains, will lead to chips with dozens of processing elements, accelerators and new NVM IPs appearing in the near future.
However, existing interconnect architectures have been designed for substrates with limited number of processing elements and conventional IPs in mind; once scaled to tomorrow’s configurations, will yield significant performance, energy, and area overheads.
The primary objective of this PhD will be to tackle the power and performance modeling of advanced interconnect architectures (NoCs primarily) and interfaces (PHYand related protocols like DFI 4.0 etc) esuring micro-architectural and Quality of Service considerations. A significant portion of the PhD will also involve laying the groundwork for an efficient translation to link hardware level abstraction (RTL) and system level abstraction (S-EAT; an imec internal system simulation platform based on gem5).The evolution towards rich, chip-level integration for diverse application domains, will lead to chips with dozens of processing elements, accelerators and new NVM IPs appearing in the near future.
Required background: Computer Science, Electrical Engineering
Type of work: 45% hardware design/simulation, 45% system design/simulation, 10% literature
Supervisor: Rudy Lauwereins
Daily advisor: Manu Perumkunnil, Timon Evenblij
The reference code for this position is 1812-38. Mention this reference code on your application form.