PhD - Leuven | More than two weeks ago
Power supply in advanced IC systems introduces serious challenges such as increased power density, lower supply voltage. IR drop, voltage noise, and electro-migration. CMOS scaling alone cannot address all these challenges.
New methodologies for effective power distribution networks (PDN) at system level should be considered that incorporate the use of on-chip as well as off-chip components, such as capacitors, inductors and voltage regulators. Furthermore, 3D circuit integration has introduced more, new opportunities for PDNs. Alternative 3D stacking techniques with different 3D interfaces and the capability of integrating passive components such as capacitors, create a very dynamic design space with plenty of design options to optimize power supply integrity.
The objective of this PhD is to investigate integrated power converters using 3D integration technology. Firstly, the PhD starts by reviewing state-of-the-art converter topologies and investigate their compatibility with the constraints and advantages of 3D integration technology. Secondly, the work focuses on exploring alternative topologies and design methodologies to maximize performance of integrated converters taking advantage of the passive components and interconnect enabled by 3D integration. The objective is to understand the relation between technology choices and circuit performance through trade-off analysis and what-if studies. Thirdly, the optimized integrated converters are realized, produced and characterized in the lab to demonstrate their capabilities.In this work, the candidate will interact with experts from industry and academia in different fields, including component and circuit modeling and simulation, technology development, and material characterization. This work involves a good understanding of models, and materials used in the semiconductor industry. This PhD will be done in a strong collaboration at imec and at KU Leuven – ESAT-MICAS.
Required background: Electrical engineering. Mixed signal design experience is an asset but not required.
Type of work: literature survey 10%, technology modeling and simulations 30%, circuit design 30%, experimental work 20%, reporting in meetings, conferences and journals 10%
Supervisor: Filip Tavernier
Daily advisor: Geert Van der Plas
The reference code for this position is 2021-034. Mention this reference code on your application form.