/Interface study of ferroelectric field-effect transistors with hafnium zirconates ferroelectrics and In-based oxide semiconductor channel

Interface study of ferroelectric field-effect transistors with hafnium zirconates ferroelectrics and In-based oxide semiconductor channel

PhD - Leuven | More than two weeks ago

Design wake-up free high polarization, high endurance, high mobility, high retention, efficient erase in Hf1-xZrxO2/In-based semiconductor oxide multilayer stacks through atomic layer deposition for FeFET applications.

A ferroelectric field-effect transistor (FeFET) combines a ferroelectric material with a semiconductor in a transistor structure. With the discovery of ferroelectricity in hafnium oxide (Boschke, 2011) and hafnium zirconate  HZO (Muller, 2012), the ferroelectric field-effect transistor has been reconsidered as a viable non-volatile memory element. Binary data can be stored in the UP and DOWN directions of ferroelectric polarization reflected in the high threshold voltage (Vth) and low Vth values that can be switched by the gate voltage (Vg). The reason is excellent scalability of the hafnium based ferroelectrics, non-destructive read-out, fast write and read speed (<10ns), and low power consumption (Khan, 2020).  It is estimated that the power consumption of FEFET is the best-in-class among all non-volatile memory technologies.  However, the state-of-the-art show a limited endurance in the range of 104 –109 switching cycles. For example, imec demonstrated a vertical 3D FEFET (similar to 3D NAND flash memories architecture) based on doped hafnia and using poly-Si as a channel,  with a 2V memory window, but the endurance was limited to 104 switching cycles (Florent, 2018). A low-k interfacial layer inevitably forms between the FE layer and the poly-Si channel. This causes reliability degradation by charge trapping and prevents low-voltage operation due to the large voltage drop at the interfacial layer. Moreover, a large thermal budget is required for the crystallization of doped hafnia and poly-Si channel. FeFETs  based on Indium-gallium-zinc-oxide (IGZO) as a channel material may solve these current challenges due to their high mobility and the lack of low-k interfacial layer formation at the ferroelectric oxide/IGZO interface. IGZO is an n-type channel material and a FET with an IGZO channel is an n-type junction-less transistor. Since minority carriers as holes are hardly generated in IGZO, the body potential is not fixed but floating, and the ferroelectric polarization charge is not balanced with the charge in the IGZO layer during the erase operation. Thus, the erase operation is not efficiently done. Recently, HZO in combination with IGZO has been proposed as low thermal budget alternative, demonstrating endurance over 108 switching cycles (Mo, 2020). Nevertheless, the properties of metal/HZO/IGZO/metal structures are not yet fully understood.

This PhD project will investigate how the structure of the HZO/IGZO stack affects the FEFET characteristics so that we can tune and improve the performance. It is expected that the HZO thickness will require scaling below 5 nm for future technology nodes. However, HZO is a multiphasic material that contains the ferroelectric (Pbca 21) orthorhombic phase, metastable tetragonal phase, as well as other non-ferroelectric phases depending on the HZO thickness, the type of dopants and  the precursors used during the Atomic Layer Deposition process (Popovici, 2022). To understand the ferroelectric response, we will investigate voltage-induced microstructural changes at both microscopic (atomic) and mesoscopic (grain structures) scales, potentially employing in-situ and multi-scale structural probing techniques. To improve the endurance, we will investigate new stack designs that improve the interface quality and increase the voltage drop across the ferroelectric layer. HZO will be optimized by varying the Hf/Zr composition, annealing conditions and thickness ratio, which are expected to influence the polar orthorhombic phase formation (thus ferroelectric polarization response) (Popovici, 2021) and overall dielectric constant in a multiphasic HZO material. With respect to In-based channel oxides, the initial studies will focus on systematic investigation of thickness and In:Ga:Zn ratio (Dekkers, 2022) to understand their impact on the memory window, program, erase, and retention of FEFET for further integration in next generation technology nodes of non-volatile ferroelectric memories.

References

T. S. Böscke et al, Appl. Phys. Lett. 99, 102903 (2011).

J. Müller et al., Symp. VLSI Tech. p. 25, (2012).

K. Florent et al., IEDM Tech. Dig., p. 43 (2018).

A. I. Khan et al, Nature Electronics, 3, p.588 (2020).

F. Mo et al., IEEE Journal of the Electron Devices Society, vol. 8, p. 717 (2020).

M. Popovici et al, Phys. Status Solidi RRL 15, p.2100033 (2021).

M. I. Popovici et al, ACS Appl. Electron. Mater. 4, p.1823, (2022).

H. F.W. Dekkers et al, ACS Appl. Electron. Mater. 4, p.1238, (2022).




Required background: Chemistry, materials science, physics

Type of work: 70% experimental, 20% electrical, 10% literature

Supervisor: Annelies Delabie

Co-supervisor: Jan Van Houdt

Daily advisor: Mihaela Ioana Popovici, Harold Dekkers

The reference code for this position is 2023-013. Mention this reference code on your application form.

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