CMOS and beyond CMOS
Discover why imec is the premier R&D center for advanced logic & memory devices. anced logic & memory devices.
Connected health solutions
Explore the technologies that will power tomorrow’s wearable, implantable, ingestible and non-contact devices.
Life sciences
See how imec brings the power of chip technology to the world of healthcare.
Sensor solutions for IoT
Dive into innovative solutions for sensor networks, high speed networks and sensor technologies.
Artificial intelligence
Explore the possibilities and technologies of AI.
More expertises
Discover all our expertises.
Be the first to reap the benefits of imec’s research by joining one of our programs or starting an exclusive bilateral collaboration.
Build on our expertise for the design, prototyping and low-volume manufacturing of your innovative nanotech components and products.
Use one of imec’s mature technologies for groundbreaking applications across a multitude of industries such as healthcare, agriculture and Industry 4.0.
Venturing and startups
Kick-start your business. Launch or expand your tech company by drawing on the funds and knowhow of imec’s ecosystem of tailored venturing support.
/Job opportunities/Investigating dry etch process induced damage to multilayer stacks used in complex memory technologies

Investigating dry etch process induced damage to multilayer stacks used in complex memory technologies

PhD - Leuven | More than two weeks ago

Exploring advanced etch techniques such as atomic layer etching on complex material alloys.

Investigating dry etch process induced damage to multilayer stacks used in complex memory technologies

Research description

There is always an ever-growing demand of fast and reliable technologies for application in data storage. High scalability, low-current, non-volatility, and adequate write endurance are some of the key aspects which need to be researched for further advancements in memory technologies. Currently SRAM (static random access memory) is a dominant contributor to data storage, but it has its drawbacks which include scalability issues arising from the use of multiple transistors, current leakage and high power consumption. One of the potential candidates to circumvent these issues are resistive-RAMs working on the principle of changing of resistance across a dielectric solid-state material. For extracting enhanced performances from such systems, new novel materials are required to be investigated from time to time. For example, phase change material systems like GeSbTe, solid-state electrolytes like GeSe and memory selectors like SiGeAsTe, amorphous or crystalline InGaZnO4 are of interest in the field of ReRAM. Therefore, their patterning into storage elements becomes a pivotal factor during the device fabrication process. The subsequent impact of the patterning process on its electrical performance also becomes crucial. While patterning these materials into storage pillars, it is necessary to ensure that the etch induced damage to the sidewall, material composition and crystallography is minimal. These process-based damages if neglected can eventually cause the devices to be either electrically shorted or perform poorly. In addition, the process needs to be scalable.

In the framework of a PhD research activity, chemical etch processes, usually used for patterning these multilayer stacks for memory technologies, need to be investigated to understand the scope of 'novel-material based' device patterning and its subsequent scalability. The etch-induced damage at the sidewall can be categorized as crystalline, interlayer diffusion- and interface-based. The first and foremost task of the student will be to carry out an extensive literature review on the process of chemical etch and provide an overview of the impacts so far on different layer compositions and structures. The PHD candidate will then be required to engage in carrying out simulations based on a well-established model, such as molecular dynamics, to understand the plasma-stack interaction systems. The goal is to understand and articulate the etchant-stack interaction as complexity is introduced into the system through the addition of multiple metallic or insulating layers of different crystallographic textures into the stack and more etchant gas components into the plasma. The interplay of redeposition and surface polymerization introduced through this needs to be explored in order to estimate the damage zone and the active region in the storage device. Softwares such as Sentaurus Sprocess, Silvaco or Intellisuite can be used for carrying out the outlined investigation in a broad scale.

A key aspect of this study will also be to correlate these theoretical results with the experimental outcomes. New etch techniques such as atomic layer etching (ALE) are available at IMEC. The ALE-based patterning is performed in cycles, wherein a cycle of substrate exposure to an etching gas to modify its surface in a controlled fashion, followed by its exposure to a removal/etch gas to remove the modified surface. Such an etch strategy will provide the student a scope 'in reality' to incorporate complexities in the plasma system systematically as has been discussed above in the simulations and can be used by the student to understand if his/her simulation outcomes remain consistent with the theoretical findings. The student will need to use advanced characterization techniques such as transmission electron microscopy (TEM), X-ray photoelectron spectroscopy (XPS) to observe and report on the experimental results. Etchant gas diffusion, any changes in the stack brought about by the etch process can be studied using these characterization techniques. Electrical measurements (for these material systems, I-V curves) may be performed on the devices patterned employing the optimal etch conditions to understand the changes in the patterned devices brought about by the etch chemistries and conditions used.

In summary, the student needs to build and present to us a vast knowledge base highlighting the significance of the chemistries and the subsequent physical dynamics that are present in the dry etch processes of complex novel materials. In order to corroborate his/her findings, it is crucial for the student to be willing to work with different individuals in a team comprising many process and device experts (processing, integration, physical characterization, modeling etc.). In such an environment, it is key that the student is open-minded and able to absorb any new knowledge and constructive criticism from his/her peers and colleagues. He/she should display good problem-solving skills, however, communicate immediately and effectively when in need for guidance.

Required background: Master’s in physics/Chemistry/Material Science, Some amount of simulation knowledge

Type of work: 45% simulation/modelling, 45% experimental, 10% literature

Supervisor: Stefan De Gendt, ,

Daily advisor: Shreya Kundu

The reference code for this position is 2020-024. Mention this reference code on your application form.

This website uses cookies for analytics purposes only without any commercial intent. Find out more here. Our privacy statement can be found here. Some content (videos, iframes, forms,...) on this website will only appear when you have accepted the cookies.