/Low-dimensional material based cold-source FET for logic Vdd scaling: Experimental Exploration

Low-dimensional material based cold-source FET for logic Vdd scaling: Experimental Exploration

PhD - Leuven | More than two weeks ago

Lower Power and Higher Efficiency: Sub-thermionic Energy-filtering Source Engineering for Steep-Slope Field Effect Transistors

Steep slope FETs are attractive alternatives to conventional thermionic-limited MOSFETs in extending the logic scaling roadmap. Low dimensional materials (1D and 2D materials) with atomically thin bodies can enable excellent electrostatic control and extreme device scaling. In addition, recent developments in sub-thermionic energy-filtering source engineering such as the Dirac-source FET [1-5] and the cold-metal FET [6] put the spotlight beyond conventional group IV, III-V and 2D materials-based tunnel-FETs and ferro-FETs. Although several single-device demonstrators have been reported in literature [1-4], aspects such as 1D-2D vs 2D-2D in sub-thermionic energy-filtering as well as fundamental understanding of channel/interface defects and their impact on steep-slope performance and variability need in-depth experimental investigation and critical assessments for potential industrial adoption. In the context of cold-source engineering, defects (e.g., dislocations, islands, grain boundary and point defects [7,8]) in/around source-channel areas, gate stack (e.g., intercalated surface contaminants and oxide traps [9]) and device fabrication related nonidealities (e.g., MX2 transfer or interactions with the environment) can significantly impact the sub-thermionic characteristics.

Low-dimensional material based cold-source FET for logic Vdd scaling: Experimental Exploration


In this PhD, the student will focus on device design, fabrication, characterization and analysis of 2D and CNT based cold-source devices to gain fundamental understanding on:

1. Energy filtering efficiency bottlenecks and showstoppers, i.e., the impact of channel/interface/oxide defects on time-zero transistor steep-slope characteristics and performance. Requires extensive room temperature and low temperature (cryostat) electrical characterizations and analysis.  

2. Vdd scaling potential: attention is needed to optimize both the steep-slope and device on-performance to realize the Vdd scaling goal. In this context, minimizing the source contact resistance at on-state is critical and equally important as the energy filtering efficiency in the sub-threshold regime. Optimization in material choice, device design and processing is the main focus.  

3. 1D-2D vs 2D-2D designs: to investigate and compare experimentally the ease of realizing steep-slope performance and their potentials for industrial adaptation. (This one can be optional)  

The student will work closely with 2D materials characterization and process engineers to adopt the imec lab-device vehicles for cold-source FET fabrication and improve the device characteristics over several learning cycles by collecting and analyzing the electrical results and correlating them with physical characterization such as AFM and SEM as well as DFT-NEGF simulations done by other team members and researchers.



[1] Qiu et al., “Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches” Science 361, 387-292 (2018). 10.1126/science.aap9195

[2] Xiao et al.,” n-Type Dirac-Source Field-Effect Transistors Based on a Graphene/Carbon Nanotube Heterojunction” Adv. Elec. Mat., 2000258 (2020)https://doi.org/10.1002/aelm.202000258

[3] Tang et al., “A Steep-Slope MoS2/Graphene Dirac-Source Field-Effect Transistor with a Large Drive Current” ACS Nano Lett. (2021) https://doi.org/10.1021/acs.nanolett.0c04657

[4] Liu et al., “Monolayer MoS2 Steep-slope Transistors with Recordhigh Sub-60-mV/decade Current Density Using Dirac-source Electron Injection” IEEE Int. Elec. Dev. Meeting (2020) 10.1109/IEDM13553.2020.9371961

[5] Wu et al., “Design Considerations for 2D Dirac-Source FETs: Device Parameters, Non-Idealities and Benchmarking” arxiv (2022) https://arxiv.org/ftp/arxiv/papers/2203/2203.11248.pdf

[6] Liu., “Switching at Less Than 60 mV/Decade with a “Cold” Metal as the Injection Source” Phys. Rev. Appl., 13, 064037 (2020) https://doi.org/10.1103/PhysRevApplied.13.064037

[7] Wu, P., Appenzeller, J., Stampfer, B., Waltl, M., Zhang, F., Illarionov, Y. Y., … Grasser, T. (2018). Characterization of Single Defects in Ultrascaled MoS 2 Field-Effect Transistors . ACS Nano, 12(6), 5368–5375. https://doi.org/10.1021/acsnano.8b00268

[8] Song, S.H., Joo, MK., Neumann, M. et al. Probing defect dynamics in monolayer MoS2 via noise nanospectroscopy. Nat Commun 8, 2121 (2017). https://doi.org/10.1038/s41467-017-02297-3

[9] Grill, A., Rzepa, G., Grasser, T., Furchi, M. M., Knobloch, T., Waltl, M., … Illarionov, Y. Y. (2016). The role of charge trapping in MoS 2 /SiO 2 and MoS 2 /hBN field-effect transistors . 2D Materials, 3(3), 035004. https://doi.org/10.1088/2053-1583/3/3/035004


Required background: Engineering Science, Semiconductor Physics, Semiconductor Devices, Physical and Electronic Characterization


Type of work: 15% theory, 15% modeling and simulation, 70% experimental

Supervisor: Kristiaan Degreve

Daily advisor: Surajit Sutar

The reference code for this position is 2023-019. Mention this reference code on your application form.

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