Low power circuit implementation of RRAM-based STDP network for neural spike sorting

Leuven
|
About a week ago

Decode the brain with brain-inspired circuits

Spike sorting is an important pattern recognition task that allows neuroscientist to extract the spiking activities of individual neurons from the raw signals collected by the neural recording devices such as neural probes and microelectrode arrays. Low power implementation of the spike sorting algorithms is becoming more and more challenging with the continuously increasing scale of neural recording. As an alternative to the conventional spike sorting scheme, spiking neural network with spike-time-dependent plasticity (STDP) learning has been studied to explore higher computational efficiency. Low power implementation of STDP network is becoming plausible thanks to the technology advances of resistive random-access memory (RRAM) devices that are promising candidates to efficiently build synapses with STDP characteristics. 

The objective of this master thesis is to study the STDP-based spike sorting schemes and explore the hardware implementation with low power CMOS circuit and commercialized RRAM devices. The student will be involved in 20% Literature study, 20% modelling and 60% circuit design and simulation.


Requirements:
- Interest and enthusiasm in mixed-signal microelectronics and machine learning
- Solid knowledge of circuit design
- Knowledge of Cadence IC design tools (Spectre, Virtuoso, etc.)
- Knowledge of resistive memory and/or neural network is a plus
- Knowledge of Matlab

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Type of project: Combination of internship and thesis, Internship, Thesis

Duration: 6-12 months

Required degree: Master of Engineering Technology, Master of Science, Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Shiwei Wang (Shiwei.Wang@imec.be)

Imec allowance will be provided.

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