/Low temperature epitaxy and germanosilicides for ultimate contact scaling

Low temperature epitaxy and germanosilicides for ultimate contact scaling

PhD - Leuven | More than two weeks ago

Unravel a fundamental limitation of ultimately scaled CMOS devices
The downscaling of metal-oxide-semiconductor transistors has dramatically increased the parasitic contribution of contacts to their output characteristics. For this reason, current device assumptions rely on aggressive contact resistivity targets, leading to intense research efforts being devoted to understanding the limits of contact scaling. Advanced contacts, required for enabling the next technologies of nanowire/nanosheet (gate-all-around) and complementary field effect transistors, necessitate cutting-edge processes involving extremely lowly resistive metal stacks combined with heavily doped epitaxial semiconductors in the source/drain regions. Suitable energy band alignments, extreme levels of control over the different interfaces and innovative integration concepts are other parameters of outmost importance.

The PhD candidate will concentrate on the fundamental understanding of the different mechanisms governing carrier transport through various metal / semiconductor (MS) interfaces targeting logic applications. He / she will experimentally validate the theoretical aspects by fabricating state-of-the-art contacts and assessing their electrical properties. A specific focus will be dedicated to the analysis of the composition profiles and material structural properties throughout the stacks. The experimental work will include a combination of advanced source/drain epitaxial growth and activation processes, the deposition of novel contact metals, (eventual) post contact formation treatments and a correlation of the (germano-)silicide phases formed at the MS interface with the achieved contact properties. The learnings from initial blanket experiments will finally be transferred to advanced device test structures. Moreover, density functional theory (DFT) and technology computer-aided design (TCAD) simulations will support the study. The activity will benefit from imec’s unique expertise in the low temperature chemical vapor deposition of highly doped n-Si and p-SiGe semiconductors using conventional and exploratory precursors. Advantage will be taken from a variety of metal deposition systems and characterization techniques available at imec premises. A constant literature survey will ensure a detailed follow-up of the latest achievements and trends in the field.

Required background: Master in material science / physics / engineering

Type of work: 50% experimental work / data analysis, 20% theoretical study, 15 % literature study, 15% dissemination

Supervisor: Clement Merckling

Daily advisor: Clement Porret, Roger Loo

The reference code for this position is 2022-002. Mention this reference code on your application form.