Leuven | More than two weeks ago
Exploring the heat dissipation impact of backside power delivery network on today's most advanced chips
Microelectronics chips are powered by a so-called power delivery network that consists of a set of interconnected metal wires that bring the power from the outside world to the transistor inside the silicon (Si) chips. Traditionally these wires are fabricated outside the transistor area, and they are part of what we called Back-End-Of-Line or BEOL. Besides providing power to the transistors, BEOL is also responsible to interconnect the different transistors in the Si chip. However, in more modern technology, where there is high requirement to increase chip functionality and speed, these set of power wires need to be relocated to shorten their distance to the active devices and to reduce the area they occupy on the chip. This new technology is called buried power rail (BPR), where the power is provided by a metal line buried in the Si chip. With this approach more space can be made free for the lines interconnecting the transistors in the BEOL.
One of the great advantages of the buried power rail is the reduction in resistance. This is a result from an increase of the wires’ aspect ratio and from their reduce length compared to the traditional power lines in the BEOL. Overall, this minimizes interconnect delay, allowing for faster operation performance.
However, bringing these power lines close to the transistor level (below), requires replacing the standard Cu metallization by different alternative metals that can withstand the thermal budget required to fabricate the transistors.
Together with the low resistance requirement and the compatibility with the thermal budget, the chosen metal needs to limit the risk of reliability degradation from metal diffusion & mechanical stress.
Typical metals that are being considered for BPR are: tungsten (W), ruthenium (Ru), molybdenum (Mo) and cobalt (Co)
All these considered metals are expected to show good reliability, but the main concern is their dissipation of heat that may affect the transistor performance. Therefore, it is a must to understand the self-heating of integrated interconnects.
The aim of this study is to investigate self-heating in these metals both experimentally and through finite element modelling (FEM).
During this study, the student will learn how to do electrical measurements in a wide set of test material in order to characterize the self-heating of different metals. In addition, the student will learn how to build up a FEM of such a test structure using a commercial FEM software. This model must be calibrated against the measurement results and can be further used to understand and support the measurement findings.
Type of project: Internship, Combination of internship and thesis
Duration: minimum 6 months
Required degree: Master of Engineering Technology, Master of Engineering Science, Master of Science
Required background: Materials Engineering, Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics, Mechanical Engineering, Electromechanical engineering
Imec allowance will be provided for students studying at a non-Belgian university.