/Micro-architectural security on Cache Coherency protocols

Micro-architectural security on Cache Coherency protocols

Leuven | More than two weeks ago

Explore the vulnerability of computer architecture paradigms for Cache coherency protocols on ManyCore HPC applications

Computer architecture paradigms are the fundamental building blocks of modern computing systems and play a crucial role in determining the performance and efficiency of computer systems. One of the critical components of these computer architecture paradigms is the cache coherency protocol, which is used to maintain a consistent view of shared data across multiple cores or processors in a computer system. 

However, the vulnerability of these computer architecture paradigms to cache coherency protocols in manycore applications is a growing concern among computer architects and researchers. This vulnerability arises due to the increasing demand for more complex and resource-intensive applications, such as high-performance computing, artificial intelligence, and machine learning.  


One of the main reasons for the vulnerability of cache coherency protocols in manycore applications is the sheer number of processors and cores that are involved in processing these applications. The parallel processing nature of manycore applications exacerbates this problem, as each processor or core operates independently and is not aware of the state of other processors or cores. This can result in incorrect data being written to the cache or incorrect data being read from the cache, leading to data corruption and data inconsistency. 

Another factor that contributes to the vulnerability of computer architecture paradigms to cache coherency protocols is the complexity of the cache coherency protocols themselves. The complexity of these protocols makes it more difficult to detect and resolve data inconsistency and corruption, increasing the latencies to handle these coherency issues. The timing channel if studied in detail could not only leak the details of the underlying architecture but also leak sensitive data that is getting computed in the application. Thus it is also important to explore innovations in Memory Hierarchy and Memory Technology in practice for manycore HPC systems to identify new timing channels or security vulnerabilities.  


Goal of this Internship: 

  1. Study timing and micro-architectural vulnerabilities in cache coherence protocols. 

  2. Trace-driven simulation to understand vulnerabilities in cache coherency protocols. 

  3. Devising experiments using micro-architectural cache attack techniques for leaking sensitive data. Timing latencies from the cache coherency protocols if observed intricately could lead to leaking sensitive data. 

  4. The ultimate goal is to propose an alternate design of cache coherency protocol which is inherently secure and robust, without compromising the performance of the overall system. 


Required background: Computer Science, Computer engineering 

Type of work: 30% architecture design, 30% threat model and analysis of the designs, 30% modeling, 10% literature 

Supervisor: Steven Latre 

Daily advisor: Sarani Bhattacharya 


Type of project: Combination of internship and thesis, Internship, Thesis

Duration: 3 to 6 months

Required degree: Master of Science, Master of Engineering Science, Master of Engineering Technology

Required background: Computer Science, Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Sarani Bhattacharya (Sarani.Bhattacharya@imec.be) and Sourav Sengupta (Sourav.Sengupta@imec.be) and Debjyoti Bhattacharjee (Debjyoti.Bhattacharjee@imec.be) and Vinay Kumar Baapanapalli Yadaiah (Vinay.Kumar.BaapanapalliYadaiah@imec.be) and Arindam Mallik (Arindam.Mallik@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.

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