CMOS and beyond CMOS
Discover why imec is the premier R&D center for advanced logic & memory devices. anced logic & memory devices.
Connected health solutions
Explore the technologies that will power tomorrow’s wearable, implantable, ingestible and non-contact devices.
Life sciences
See how imec brings the power of chip technology to the world of healthcare.
Sensor solutions for IoT
Dive into innovative solutions for sensor networks, high speed networks and sensor technologies.
Artificial intelligence
Explore the possibilities and technologies of AI.
More expertises
Discover all our expertises.
Be the first to reap the benefits of imec’s research by joining one of our programs or starting an exclusive bilateral collaboration.
Build on our expertise for the design, prototyping and low-volume manufacturing of your innovative nanotech components and products.
Use one of imec’s mature technologies for groundbreaking applications across a multitude of industries such as healthcare, agriculture and Industry 4.0.
Venturing and startups
Kick-start your business. Launch or expand your tech company by drawing on the funds and knowhow of imec’s ecosystem of tailored venturing support.
/Job opportunities/Modeling of advanced charge trap flash memory

Modeling of advanced charge trap flash memory

PhD - Leuven | More than two weeks ago

Develop a fundamental modeling approach to increase understanding of scaled charge trap flash memories

Memories are an essential building block for all electronic systems. Non-volatile data storage is leading the electronics industry today, accounting for over 80% of all transistors manufactured. The most prominent non-volatile technology is 3-dimensional NAND flash memory, which is integrated into an ever-expanding and diverse range of applications, such as mobile phones, personal computers, data centers and machine learning. Memory densities are relentlessly increasing: advanced 3-D NAND flash technologies have reached bit densities of 5 Gigabit per mm2 and continued scaling is projected to reach densities of 256 Gb/mm2 by 2028.

Despite the wide adoption of 3-D NAND flash across the memory market, there is still a lack of fundamental understanding of the underlying operational mechanisms. Current flash memories rely on the trapping of charge in a SiN layer, injected by quantum tunneling from the channel or the gate. This is an interplay of intricate physical processes, for which there is not yet a unified physics-based modeling approach. Existing modeling efforts are highly empirical and are narrowly calibrated to fabricated devices. This limits their range of applicability, making them poorly suited for predictive simulations of future scaled devices. It also prevents the investigation of other promising flash architectures that might enable an extension of the scaling roadmap, such as the 3D trench based flat cell architecture.

Hence, the goal of this PhD is to increase fundamental device understanding in charge trapping based memories through the development of physics-based modeling approaches and the validation of these models through test structure characterization. The first step is a thorough literature study to get acquainted with the state-of-the-art in 3-D NAND modeling and to delineate the current gaps in understanding. Second is the identification of the most relevant physical mechanisms and the selection of (quantum mechanical) models to capture them. Examples of some of these mechanisms are trap-assisted-tunneling, charge trapping and emission, trap-to-band-tunneling and field-enhanced insulator transport. Next, a modeling framework will be developed and implemented in collaboration with our modeling experts. After the first implementation, test structures can be defined and characterized to experimentally validate the assumptions that were made during the modeling. In these steps, close collaboration with our integration engineers in the 300mm fabrication line is expected. Finally, the understanding gained from the implemented model can serve to improve existing empirical models, to investigate the scaling impact on 3-D NAND memories and to explore new device architectures.

For this ambitious PhD project, imec is soliciting enthusiastic PhD candidates. Since 3-D NAND flash technology is so prevalent, this research has the potential to have a worldwide impact on devices that people use every day. The project requires a strong background in semiconductor physics, electrical engineering, and notions of material science. It offers you a combination of fundamental modeling, test structure design and characterization, with a strong connection to practical device challenges. In the flash team at imec, you will work in a world-class research environment, with close contact to market-leading industrial partners.

Required background: Solid-state Physics, Electrical Engineering, Nanotechnology

Type of work: 15% literature, 60% modeling and implementation, 25% design and measurements

Supervisor: Michel Houssa

Co-supervisor: Jan Van Houdt

Daily advisor: Devin Verreck, Antonio Arreghini

The reference code for this position is 2021-014. Mention this reference code on your application form.

This website uses cookies for analytics purposes only without any commercial intent. Find out more here. Our privacy statement can be found here. Some content (videos, iframes, forms,...) on this website will only appear when you have accepted the cookies.